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IS61C25616AL

256K x 16 HIGH-SPEED CMOS STATIC RAM

Integrated Silicon Solution 

IS61C25616AL IS61C25616AS

IS64C25616AL IS64C25616AS

WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2)

ADDRESS

OE

t WC

VALID ADDRESS

t HA

CE LOW

WE

t SA

UB, LB

DOUT

DATA UNDEFINED

DIN

t AW

t PWE1

t PBW

t HZWE

HIGH-Z

t LZWE

t SD

t HD

DATAIN VALID

UB_CEWR2.eps

WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1)

ADDRESS

OE LOW

t WC

VALID ADDRESS

t HA

CE LOW

WE

t SA

t AW

t PWE2

t PBW

UB, LB

DOUT

DATA UNDEFINED

t HZWE

HIGH-Z

t LZWE

t SD

t HD

DIN

DATAIN VALID

UB_CEWR3.eps

Notes:

1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if OE ≥ VIH.

10

Integrated Silicon Solution, Inc. — www.issi.com

Rev. C

03/21/2008

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