IR3Y48A1 Просмотр технического описания (PDF) - Sharp Electronics

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IR3Y48A1

CCD Signal Process & Digital Interface IC

Sharp Electronics 

High-speed Black Level Cancellation

The IR3Y48A1 has the function that settles a black

level at high speed. The function that increases a

settling speed in a fixed period from the access to

the serial interface can become available by the

register setting. This function increases the gain of

the settling DAC in a fixed period, and it increases

the charge/discharge current to the OBCAP

capacitor.

The black level boost function is set with the Mode

(3) register, D3, D2, D1 and D0 bits. The default

setting is always low gain (D3 = D2 = D1 = D0 = 0).

By setting the register D2, D1 and D0 bits, the gain

becomes high during 1 to 7 times of OBP pulse

period after any access to the serial interface. After

that period, the gain returns to low.

When setting D3 to "1", the gain is always high.

The CSN signal becomes the starting point of the

OBP pulse count.

The right figure of "Black Loop Settling Gain Boost

Timing" is the timing chart when the boost control is

on and the boost period is set to 3. The left figure

of "Black Level Settling" below is the image of the

settlement when the gain is high or low.

IR3Y48A1

Black Level Boost

CDS +

PGA

OBCAP

OBP

DAC

10-bit

ADC

Compare

D0 to D9

IDAC

Low Gain : Small

High Gain : Large

Black Level Register

Black Loop Settling Gain Boost Timing

CSN

OBP

TSUCS

THCS

Counter

Black Loop

Gain

0123

3 0 1 2 01 2

High gain Low gain

High gain

Gain boost function ON (Mode (3) D3 = 1)

High gain for 3 pulses (Mode (3) D2 = 0, D1 = 1, D0 = 1)

CSN

OBP

DOUT

Black

Code

Black

Offset

High Gain

CSN

OBP

Low Gain

Black Level

Target Value

(Change Register Value)

Area CCD

CSN & OBP TIMING

PARAMETER

CSN setup time

CSN hold time

Black Level Settling

SYMBOL

TSUCS

THCS

CONDITIONS

10

MIN.

0

5

TYP.

MAX.

UNIT

µs

clock

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