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INT5130CS

Integrated Powerline MAC/PHY Transceiver

Unspecified 

INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet

General Purpose Serial Interface (GPSI)

These pins are multiplexed with the MII pins and are selected when MII_GSPI_N signal is at VSS.

GPSI_RXD

Output

GPSI Receive Data

This signal carries data received from the powerline

and delivers to the external host. Data is driven on

the falling edge of the GPSI_RXCLK.

GPSI_RXCLK

Output

GPSI Receive Clock

This signal is the timing reference for the serial data

transfer from the INT5130 to the external host. This

clock operates at 10 MHz.

GPSI_TXD

Input

GPSI Transmit Data

This signal carries data transmitted from the external

host to the INT5130 for transmission over the

powerline. Data is latched on the falling edge of the

GPSI_TXCLK.

GPSI_TXCLK

Output

GPSI Transmit Clock

This signal is the timing reference for the serial data

transfer from the external host to the INT5130. This

clock operates at 10 MHz.

GPSI_RXEN

Output

GPSI Receive Enable

Indicates valid data is on the GPSI_RXD line.

GPSI_TXEN

Input

GPSI Transmit Enable

Indicates when the external host is providing valid

data on GPSI_TXD.

GPSI_TXBSY

Output

GPSI Transmit Busy

The GPSI Transmit Busy signal is asserted within

120 GPSI clocks after GPSI_TXEN indicates a TX

frame is being sent by the local host. GPSI_TXBSY

stays true until the entire TX frame is loaded into an

internal buffer AND a new buffer is allocated to the

GPSI TX interface. This signal should be monitored

by the GPSI TX host. A new GPSI TX frame should

not be sent until GPSI_TXBSY returns to false to

prevent TX buffer overflows.

GPSI_TXBSY is an asynchronous output signal.

GPSI_COL

Output

GPSI Collision Detect

This signal is driven false in GPSI mode.

SPI Slave Port

Selected when MDI_SPIS_N signal is at VSS.

SPIS_SDO

Output

SPI Slave Data Out

SPI data from the INT5130 to the external host.

SPIS_SDI

Input

SPI Slave Data In

SPI data from the external host to the INT5130.

This pin is shared with the MDI_ADRSEL[1].

SPIS_SCLK

Input

SPI Slave Clock

Timing reference signal for SPI_SDI and SPI_SDO.

SPIS_CS_N

Input

SPI Slave Chip Select

Enables SPI data transfers on the INT5130. This

pin is shared with the MDI_ADRSEL[0].

INTELLON CONFIDENTIAL

6

Rev 8.1

ADVANCE INFORMATION

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