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INT5130CS

Integrated Powerline MAC/PHY Transceiver

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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet

Pin Descriptions by Group

Signal Name

I/O Pad Description

Signal Description

Media Independent Interface (MII)

These pins are multiplexed with the GPSI pins and are selected when MII_GSPI_N signal is at VDD.

MII_RX[3:0]

Output

MII Receive Data.

Data is transferred from the INT5130 to the external

MAC across these four lines one nibble at a time.

MII_RXCLK

Output

MII Receive Clock

The receive clock outputs a continuous 25MHz clock

to the external MAC.

MII_RXDV

Output

MII Receive Data Valid

This signal indicates that the incoming data on the

MII_RX[3:0] pins are valid.

MII_RX_ER

Output

MII Receive Error

This signal indicates to the external MAC that an

error has occurred during the frame reception.

MII_TX[3:0]

Input

MII Transmit Data

Data is transferred to the INT5130 from the external

MAC across these four lines one nibble at a time.

MII_TXCLK

Output

MII Transmit Clock

The transmit clock outputs a continuous 25MHz

clock to the external MAC.

MII_TXEN

Input

MII Transmit Enable

This signal indicates to the INT5130 that valid data

is present on the MII_TX[3:0] pins.

MII_TX_ER

Input

MII Transmit Error

MII_TX_ER is activated by the external host

controller when an error condition is detected during

packet transmission. The INT5130 will ignore any

MII transmission within which MII_TX_ER is

asserted. MII_TX_ER is ignored if MII_TXEN is not

asserted.

MII_CRS

Output

MII Carrier Sense

This signal indicates to the external host that traffic

is present on the powerline and the host should wait

until the signal goes invalid before sending additional

data. This signal is an asynchronous output signal.

MII_COL

Output

MII Collision Detect

This signal indicates to the external host that a

collision has occurred on the MII interface. This

signal is an asynchronous output signal.

MII Management Data Interface (MDI)

These pins are multiplexed with the SPIS_SDO and SPIS_SCLK signals and are selected when MDI_SPIS_N is at VDD.

MII_MDIO

Input/Output

MII Management Data Input/Output

This bi-directional signal carries the data for the

Management Data Interface.

MII_MDCLK

Input

MII Management Data Clock

Clock reference for the MII_MDIO signal.

INTELLON CONFIDENTIAL

5

Rev 8.1

ADVANCE INFORMATION

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