IDT82V2084 Просмотр технического описания (PDF) - Integrated Device Technology

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IDT82V2084

QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

3.8 ERROR DETECTION/COUNTING AND INSERTION ...................................................... 29

3.8.1 DEFINITION OF LINE CODING ERROR ............................................................... 29

3.8.2 ERROR DETECTION AND COUNTING ................................................................ 29

3.8.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 30

3.9 LINE DRIVER FAILURE MONITORING ........................................................................... 30

3.10 MCLK AND TCLK ............................................................................................................. 31

3.10.1 MASTER CLOCK (MCLK) ...................................................................................... 31

3.10.2 TRANSMIT CLOCK (TCLK).................................................................................... 31

3.11 MICROCONTROLLER INTERFACES ............................................................................. 32

3.11.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 32

3.11.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 32

3.12 INTERRUPT HANDLING .................................................................................................. 33

3.13 5V TOLERANT I/O PINS .................................................................................................. 33

3.14 RESET OPERATION ........................................................................................................ 33

3.15 POWER SUPPLY ............................................................................................................. 33

4 PROGRAMMING INFORMATION .............................................................................................. 34

4.1 REGISTER LIST AND MAP ............................................................................................. 34

4.2 REGISTER DESCRIPTION .............................................................................................. 36

4.2.1 GLOBAL REGISTERS............................................................................................ 36

4.2.2 JITTER ATTENUATION CONTROL REGISTER ................................................... 37

4.2.3 TRANSMIT PATH CONTROL REGISTERS........................................................... 38

4.2.4 RECEIVE PATH CONTROL REGISTERS ............................................................. 40

4.2.5 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 42

4.2.6 INTERRUPT CONTROL REGISTERS ................................................................... 45

4.2.7 LINE STATUS REGISTERS ................................................................................... 48

4.2.8 INTERRUPT STATUS REGISTERS ...................................................................... 51

4.2.9 COUNTER REGISTERS ........................................................................................ 52

4.2.10 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 53

5 IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 54

5.1 JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 55

5.2 JTAG DATA REGISTER ................................................................................................... 55

5.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 55

5.2.2 BYPASS REGISTER (BR)...................................................................................... 55

5.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 55

5.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 56

6 TEST SPECIFICATIONS ............................................................................................................ 58

7 MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 70

7.1 SERIAL INTERFACE TIMING .......................................................................................... 70

7.2 PARALLEL INTERFACE TIMING ..................................................................................... 71

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