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IDT82V2084

QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

Table-1 Pin Description (Continued)

Name

RD1/RDP1

RD2/RDP2

RD3/RDP3

RD4/RDP4

CV1/RDN1

CV2/RDN2

CV3/RDN3

CV4/RDN4

RCLK1

RCLK2

RCLK3

RCLK4

MCLK

MCLKS

LOS1

LOS2

LOS3

LOS4

P/S

Type TQFP128

Description

Output

93 RDn: Receive Data for Channel 1~4

87 In Single Rail Mode, the NRZ receive data is output on these pins. Data is decoded according to AMI, HDB3 or B8ZS line code

77 rules. The active level on RDn pin is selected by the RD_INV bit (RCF0, 07H...).

71

CVn: Code Violation for Channel 1~4

92 In Single Rail Mode, the BPV/CV errors in received data streams will be reported by driving pin CVn to high level for a full clock

86 cycle. The B8ZS/HDB3 line code violation can be indicated when the B8ZS/HDB3 decoder is enabled. When AMI decoder is

76 selected, the bipolar violation can be indicated.

70

RDPn/RDNn: Positive/Negative Receive Data for Channel 1~4

In Dual Rail Mode with Clock & Data Recovery (CDR), these pins output the NRZ data with the recovered clock. An active level

on RDPn indicates the receipt of a positive pulse on RTIPn/RRINGn while an active level on RDNn indicates the receipt of a neg-

ative pulse on RTIPn/RRINGn. The active level on RDPn/RDNn is selected by the RD_INV bit (RCF0, 07H...). When CDR is

disabled, these pins directly output the raw RZ sliced data. The output data on RDn and RDPn/RDNn is updated on the active

edge of RCLKn.

Output

94 RCLKn: Receive Clock for Channel 1~4

88 These pins output 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode receive clock. Under LOS conditions, if AISE bit

78 (MAINT0, 0AH...) is ‘1’, RCLKn is derived from MCLK.

72 In clock recovery mode, these pins provide the clock recovered from the signal received on RTIPn/RRINGn. The receive data

(RDn in Single Rail Mode or RDPn/RDNn in Dual Rail Mode) is updated on the active edge of RCLKn. The active edge is

selected by the RCLK_SEL bit (RCF0, 07H...).

If clock recovery is bypassed, RCLKn is the exclusive OR(XOR) output of the Dual Rail sliced data RDPn and RDNn. This signal

can be used in the applications with external clock recovery circuitry.

Input

10 MCLK: Master Clock

MCLK is an independent, free-running reference clock. It is a single reference for all operation modes and provides selectable

1.544 MHz or 37.056 MHz for T1/J1 operating mode, while 2.048 MHz or 49.152 MHz for E1 operating mode.

The reference clock is used to generate several internal reference signals:

• Timing reference for the integrated clock recovery unit.

• Timing reference for the integrated digital jitter attenuator.

• Timing reference for microcontroller interface.

• Generation of RCLKn signal during a loss of signal condition.

• Reference clock during Transmit All Ones (TAO) and all zeros condition. When sending PRBS/QRSS or Inband Loopback

code, either MCLK or TCLKn can be selected as the reference clock.

• Reference clock for ATAO and AIS.

The loss of MCLK will turn all the four TTIP/TRING into high impedance status.

Input

40 MCLKS: Master Clock Select

If 2.048 MHz (E1) or 1.544 MHz (T1/J1) is selected as the MCLK, this pin should be connected to ground; and if the 49.152 MHz

(E1) or 37.056 MHz (T1/J1) is selected as the MCLK, this pin should be pulled high.

Output

128 LOSn: Loss of Signal Output for Channel 1~4

1 These pins are used to indicate the loss of received signals. When LOSn pin becomes high, it indicates the loss of received sig-

2 nals in channel n. The LOSn pin will become low automatically when valid received signal is detected again. The criteria of loss

3 of signal are described in 3.5 LOS AND AIS DETECTION.

Input

Control Interface

8 P/S: Parallel or Serial Control Interface Select

Level on this pin determines which control mode is selected to control the device as follows:

P/S

Control Interface

High

Parallel Microcontroller Interface

Low

Serial Microcontroller Interface

The serial microcontroller interface consists of CS, SCLK, SDI, SDO and SCLKE pins. Parallel microcontroller interface consists

of CS, A[7:0], D[7:0], DS/RD and R/W/WR pins. The device supports non-multiplexed parallel interface as follows:

P/S, INT/MOT

10

11

Microcontroller Interface

Motorola non-multiplexed

Intel non-multiplexed

10

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