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IDT821034

QUAD PCM CODEC WITH PROGRAMMABLE GAIN

Integrated Device Technology 

IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN

INDUSTRIAL TEMPERATURE RANGE

Bit

CR.7 Register Indicator

CR.6 Mode Select 1

CR.5 Mode Select 0

Name

CODEC Mode (CR.6 = ‘0’)

CR.4

SLIC/Gain Mode (CR.6 = ‘1’)

Timing Mode Select

SLIC/Gain Mode Select

Value

00

01

10

11

0

1

0

1

Description

Always ‘1’

µ-Law CODEC Mode (This is global setting for all channels.)

A-Law CODEC Mode (This is global setting for all channels.)

SLIC/Gain Mode

Reserved (This mode should not be programmed for normal operation.)

Non-delay Mode (This is global setting for all channels.)

Delay Mode (This is global setting for all channels.)

Gain Mode

SLIC Mode

CR.3 Channel Address 1

CR.2 Channel Address 0

00 Select Channel 0 for CODEC or SLIC programming

01 Select Channel 1 for CODEC or SLIC programming

10 Select Channel 2 for CODEC or SLIC programming

11 Select Channel 3 for CODEC or SLIC programming

CODEC Mode (CR.6 = ‘0’)

Transmitter Select

Receiver Select

00 Channel power down

01 Channel power up with receive time slot assignment

10 Channel power up with transmit time slot assignment

11 Channel power up with both receive and transmit time slot assignment

CR.1

SLIC Mode (CR.6 = ‘1’, CR.4 = ‘1’)

I/O_1 Configuration

I/O_0 Configuration

CR.0

CR.1: Transmit/Receive

Select

00 Configure I/O_1 as an output pin and I/O_0 as an output pin

01 Configure I/O_1 as an output pin and I/O_0 as an input pin

10 Configure I/O_1 as an input pin and I/O_0 as an output pin

11 Configure I/O_1 as an input pin and I/O_0 as an input pin

0 Receive gain will be adjusted

1 Transmit gain will be adjusted

Gain Mode (CR.6 = ‘1’, CR.4 = ‘0’)

CR.0: MSB/LSB Select

0 Indicates the following 8 bits contain the 7 Least Significant bits of gain

adjustment coefficient

1 Indicates the following 8 bits contain the 7 Most Significant bits of gain

adjustment coefficient

Table 1. Description of Configuration Register

Bit

Name

7

Register Indicator

6

Time Slot Bit 6

5

Time Slot Bit 5

4

Time Slot Bit 4

3

Time Slot Bit 3

2

Time Slot Bit 2

1

Time Slot Bit 1

0

Time Slot Bit 0

Description

Always ‘0’

Bit 6-0 indicate which time slot is selected for the transmit/receive channel. Time

Slot 0 is aligned to FS.

Table 2. Definition of Time Slot Register

BCLK Frequency

Number of Time Slot

512 kHz

8

1.544 MHz

24

2.048 MHz

32

4.096 MHz

64

Table 3. Relationship between BCLK Frequency and Time Slot Number

8.192 MHz

128

7

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