IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ± 10%, TA = -55°C to +125°C and 0°C to +70°C)
–35
Symbol Parameter
Min. Max.
Read Cycle
tRC
Read Cycle Time
35
—
tAA
tACS(2)
Address Access Time
Chip Select Access Time
—
35
—
35
tOE
Output Enable Access Time
—
20
tOH
tCLZ(1)
tCHZ(1)
tOLZ(1)
tOHZ(1)
tPU(1)
tPD(1)
Output Hold From Address Change
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Chip Select to Power-Up Time
Chip Disable to Power-Down Time
3
—
3
—
—
20
3
—
—
20
0
—
—
50
tSOP
SEM Flag Update Pulse (OE or SEM)
15
—
Write Cycle
tWC
tCW(2)
Write Cycle Time
Chip Select to End-of-Write
35
—
30
—
tAW
tAS1(3)
Address Valid to End-of-Write
Address Set-up to Write Pulse Time
30
—
5
—
tAS2
Address Set-up to CS Time
0
—
tWP
tWR(4)
Write Pulse Width
Write Recovery Time
30
—
0
—
tDW
tDH(4)
tOHZ(1)
tWHZ(1)
tOW(1, 4)
Data Valid to End-of-Write
Data Hold Time
Output Disable to Output in High-Z
Write Enable to Output in High-Z
Output Active from End-of-Write
25
—
0
—
—
20
—
20
0
—
tSWRD
SEM Flag Write to Read Time
15
—
tSPS
SEM Flag Contention Window
15
—
Port-to-Port Delay Timing
tWDD(5) Write Pulse to Data Delay
tDDD(5) Write Data Valid to Read Data Valid
—
60
—
45
NOTES:
1. This parameter is guaranteed by design but not tested.
2. To access RAM CS ≤ VIL and SEM ≥ VIH. To access semaphore, CS ≥ VIH and SEM ≤ VIL.
3. tAS1= 0 if R/W is asserted LOW simultaneously with or after the CS LOW transition.
4. For CS controlled write cycles, tWR= 5ns, tDH= 5ns, tOW= 5ns.
5. Port-to-Port delay through the RAM cells from the writing port to the reading port.
–40
Min. Max.
40
—
—
40
—
40
—
25
3
—
3
—
—
20
3
—
—
20
0
—
—
50
15
—
40
—
35
—
35
—
5
—
0
—
35
—
0
—
30
—
0
—
—
20
—
20
0
—
15
—
15
—
—
65
—
50
–50
Min. Max.
50
—
—
50
—
50
—
30
3
—
3
—
—
25
3
—
—
25
0
—
—
50
15
—
50
—
40
—
40
—
5
—
0
—
40
—
0
—
35
—
0
—
—
25
—
25
0
—
15
—
15
—
—
70
—
55
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2804 tbl 09
7.5
5