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IDT54FCT388915T70PYB Просмотр технического описания (PDF) - Integrated Device Technology

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IDT54FCT388915T70PYB
IDT
Integrated Device Technology IDT
IDT54FCT388915T70PYB Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Condition(1)
Min.*
Max.*
Unit
tRISE/FALL
All Outputs
tPULSE WIDTH (3)
Q, Q, Q/2 outputs(3)
tPULSE WIDTH
2Q Output(3)
Rise/Fall Time
(between 0.8V and 2.0V)
Output Pulse Width
Q0-Q4, Q5, Q/2, @ 1.5V
Output Pulse Width
2Q @ 1.5V
Load = 50to
0.2(2)
1.5
ns
VCC/2, CL = 20pF
Load = 50to 0.5tCYCLE – 0.5(5) 0.5tCYCLE + 0.5(5) ns
VCC/2, CL = 20pF
0.5tCYCLE – 0.7(5) 0.5tCYCLE + 0.7(5) ns
tPD
SYNC input to FEEDBACK delay
Load = 50to
–0.5
SYNC-FEEDBACK(3) (measured at SYNC0 or 1 and FEEDBACK VCC/2, CL = 20pF
input pins)
0.1µF from LF to
Analog GND(5)
+0.5
ns
tSKEWr
(rising)(3,4)
Output to Output Skew
between outputs 2Q, Q0-Q4,
Load = 50to
VCC/2, CL = 20pF
250
ps
Q/2 (rising edges only)
tSKEWf
(falling)(3,4)
tSKEWall (3,4)
tLOCK(6)
Output to Output Skew
between outputs Q0-Q4 (falling edges only)
Output to Output Skew
2Q, Q/2, Q0-Q4 rising, Q5 falling
Time required to acquire
250
ps
350
ps
1(2)
10
ms
Phase-Lock from time
SYNC input signal is received
tPZH
Output Enable Time
tPZL
OE/RST (LOW-to-HIGH) to Q, 2Q, Q/2, Q
tPHZ
Output Disable Time
tPLZ
OE/RST (HIGH-to-LOW) to Q, 2Q, Q/2, Q
3(2)
14
ns
3(2)
14
ns
GENERAL AC SPECIFICATION NOTES:
3052 tbl 08
* PRELIMINARY.
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage.
5. tCYCLE = 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run.
6. With VCC fully powered-on and an output properly connected to the FEEDBACK pin. tLOCK Max. is with C1 = 0.1µF, tLOCK Min. is with C1 = 0.01µF. (Where
C1 is loop filter capacitor shown in Figure 2).
9.8
5

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