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IDT72V3622
(Rev.:2015)

3.3 VOLT CMOS SyncBiFIFOTM 256 x 36 x 2 512 x 36 x 2 1,024 x 36 x 2

Integrated Device Technology 

IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS

Symbol

Name

I/O

Description

A0-A35

AEA

AEB

AFA

AFB

B0 - B35

CLKA

Port A Data

Port A Almost-

Empty Flag

Port B Almost-

Empty Flag

Port A Almost-

Full Flag

Port B Almost-

Full Flag

Port B Data

Port A Clock

CLKB

Port B Clock

CSA

CSB

EFA/ORA

Port A Chip

Select

Port B Chip

Select

Port A Empty/

Output Ready

Flag

EFB/ORB Port B Empty/

Output Ready

Flag

ENA

ENB

FFA/IRA

Port A Enable

Port B Enable

Port A Full/

Input Ready

Flag

FFB/IRB

Port B Full/

Input Ready

Flag

FWFT

First Word Fall

Through Mode

FS1, FS0 FlagOffset

Selects

I/0

O

(Port A)

O

(Port B)

O

(Port A)

O

(Port B)

I/O

I

I

I

I

O

O

I

I

O

O

I

I

36-bit bidirectional data port for side A.

Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is

less than or equal to the value in the Almost-Empty A Offset register, X2.

Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is

less than or equal to the value in the Almost-Empty B Offset register, X1.

Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in

FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.

Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty locations in

FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2.

36-bit bidirectional data port for side B.

CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or

coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH

transition of CLKA.

CLKB is a continuous clock that synchronizes all data transfers through port Band can be asynchronous or

coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are synchronized to the LOW-to-HIGH

transition of CLKB.

CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write on port A. The A0-A35

outputs are in the high-impedance state when CSA is HIGH.

CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The

B0- B35 outputs are in the high-impedance state when CSB is HIGH.

This is a dual function pin. In the IDT Standard mode, the EFA function is selected. EFA indicates

whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA

indicates the presence of valid data on A0-A35 outputs, available for reading. EFA/ORA is synchronized

to the LOW-to-HIGH transition of CLKA.

This is a dual function pin. In the IDT Standard mode, the EFB function is selected. EFB indicates

whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB

indicates the presence of valid data on B0-B35 outputs, available for reading. EFB/ORB is synchronized to

the LOW-to-HIGH transition of CLKB.

ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.

ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.

This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates whether

or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA indicates whether or

not there is space available for writing to the FIFO1 memory. FFA/IRA is synchronized to the LOW-to-

HIGH transition of CLKA.

This is a dual function pin. In the IDT Standard mode, the FFB function is selected. FFB indicates whether

or not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB indicates whether or

not there is space available for writing to the FIFO2 memory. FFB/IRB is synchronized to the LOW-to-

HIGH transition of CLKB.

This pin selects the timing mode. A HIGH on FWFT selects IDT Standard mode, a LOW selects First

Word Fall Through mode. Once the timing mode has been selected, the level on FWFT must be static

throughout device operation.

A LOW-to-HIGH transition of the FIFO Reset input latches the values of FS0 and FS1. If either FS0 or

FS1 is HIGH when the FIFO Reset input goes HIGH, one of three preset values is selected as the

offset for FIFOs Almost-Full and Almost-Empty flags. If both FIFOs are reset simultaneously and both

FS0 and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to FIFO1 load the Almost-

Empty and Almost-Full offsets for both FIFOs.

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