IDT72V3624(2015) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT72V3624
(Rev.:2015)

3.3 VOLT CMOS SyncBiFIFO WITH BUS-MATCHING

Integrated Device Technology 

IDT72V3624/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING

256 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY

VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

Commercial: VCC = 3.3V +/- 0.30V; for 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V ; TA = 0°Cto +70°C; JEDEC JESD8-A compliant

Symbol

fS

tCLK

tCLKH

tCLKL

tDS

tENS1

tENS2

tRSTS

tFSS

tBES

tSPMS

tSDS

tSENS

tFWS

tDH

tENH

tRSTH

tFSH

tBEH

tSPMH

tSDH

tSENH

tSPH

tSKEW1(3)

tSKEW2(3,4)

Parameter

Clock Frequency, CLKA or CLKB

Clock Cycle Time, CLKA or CLKB

Pulse Duration, CLKA or CLKB HIGH

Pulse Duration, CLKA and CLKB LOW

Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑

Setup Time CSA before CLKA↑; CSB before CLKB↑

Setup Time ENA, W/RA and MBA before CLKA↑; ENB, W/RB and MBB

before CLKB↑

Setup Time, MRS1, MRS2, PRS1, or PRS2 LOW before CLKA↑ or CLKB↑(2)

Setup Time, FS0 and FS1 before MRS1 and MRS2 HIGH

Setup Time, BE/FWFT before MRS1 and MRS2 HIGH

Setup Time, SPM before MRS1 and MRS2 HIGH

Setup Time, FS0/SD before CLKA↑

Setup Time, FS1/SEN before CLKA↑

Setup Time, BE/FWFT before CLKA↑

Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑

Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and

MBB after CLKB↑

Hold Time, MRS1, MRS2, PRS1 or PRS2 LOW after CLKA↑ or CLKB↑(2)

Hold Time, FS0 and FS1 after MRS1 and MRS2 HIGH

Hold Time, BE/FWFT after MRS1 and MRS2 HIGH

Hold Time, SPM after MRS1 and MRS2 HIGH

Hold Time, FS0/SD after CLKA↑

Hold Time, FS1/SEN HIGH after CLKA↑

Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH

Skew Time between CLKA↑ and CLKB↑ for EFA/ORA, EFB/ORB, FFA/IRA,

and FFB/IRB

Skew Time between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB

IDT72V3624L10(1) IDT72V3624L15

IDT72V3644L10(1) IDT72V3644L15

Min. Max. Min. Max. Unit

—

100

—

66.7 MHz

10

—

15

—

ns

4.5

—

6

—

ns

4.5

—

6

—

ns

3

—

4

—

ns

4

—

4.5

—

ns

3

—

4.5

—

ns

5

—

5

7.5

—

7.5

7.5

—

7.5

7.5

—

7.5

3

—

4

3

—

4

0

—

0

0.5

—

1

0.5

—

1

—

ns

—

ns

—

ns

—

ns

—

ns

—

ns

—

ns

—

ns

—

ns

4

—

4

2

—

2

2

—

2

2

—

2

0.5

—

1

0.5

—

1

2

—

2

5

—

7.5

—

ns

—

ns

—

ns

—

ns

—

ns

—

ns

—

ns

—

ns

12

—

12

—

ns

NOTES:

1. For 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V; TA = 0° to +70°C; JEDEC JESD8-A compliant.

2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.

4. Design simulated, not tested.

5. Industrial temperature range is available by special order.

8

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