IDT72V3624(2015) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT72V3624
(Rev.:2015)

3.3 VOLT CMOS SyncBiFIFO WITH BUS-MATCHING

Integrated Device Technology 

IDT72V3624/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING

256 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS (CONTINUED)

Symbol

Name

I/O

Description

FS1/SEN Flag Offset Select 1/

Serial Enable,

FS0/SD Flag Offset Select 0/

Serial Data

MBA Port A Mailbox

Select

I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master

Reset, FS1/SEN and FS0/SD, together with SPM, select the flag offset programming method. Three

offset register programming methods are available: automatically load one of three preset values (8, 16,

or 64), parallel load from Port A, and serial load.

I When serial load is selected for flag offset register programming, FS1/SEN is used as an enable

synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA

load the bit present on FS0/SD into the X and Y registers. The number of bit writes required to program

the offset registers is 32 for the 72V3624, and 40 for the 72V3644. The first bit write stores the Y-register

(Y1) MSB and the last bit write stores the X-register (X2) LSB.

I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35

outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level

selects FIFO2 output register data for output.

MBB Port B Mailbox

Select

I A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35

outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level

selects FIFO1 output register data for output.

MBF1 Mail1 Register

Flag

O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to

the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition

CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or

Partial Reset of FIFO1.

MBF2 Mail2 Register

Flag

O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to

the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of

CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or

Partial Reset of FIFO2.

MRS1 FIFO1 Master

Reset

I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the

Port B output register to all zeroes. A LOW-to-HIGH transition on MRS1 selects the programming method

(serial or parallel) and one of three programmable flag default offsets for FIFO1 and FIFO2. It also configures

Port B for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH

transitions of CLKB must occur while MRS1 is LOW.

MRS2 FIFO2 Master

Reset

I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the

Port A output register to all zeroes. A LOW-to-HIGH transition on MRS2, toggled simultaneously with MRS1,

selects the programming method (serial or parallel) and one of the programmable flag default offsets for

FIFO2. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while

MRS2 is LOW.

PRS1 FIFO1 Partial

Reset

I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the

Port B output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement,

programming method (serial or parallel), and programmable flag settings are all retained.

PRS2 FIFO2 Partial

Reset

I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the

Port A output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement,

programming method (serial or parallel), and programmable flag settings are all retained.

SIZE Bus Size Select

I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is

HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian

arrangement for Port B. The level of SIZE must be static throughout device operation.

SPM Serial Programming I A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin selects parallel

Mode

programming or default offsets (8, 16, or 64).

W/RA Port-A Write/

Read Select

I A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition

of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.

W/RB Port-B Write/

Read Select

I A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH transition

of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.

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