IDT72V3643L15PF Просмотр технического описания (PDF) - Integrated Device Technology
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IDT72V3643L15PF
Integrated Device Technology
IDT72V3643L15PF Datasheet PDF : 28 Pages
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IDT72V3623/72V3633/72V3643 CMOS 3.3V SyncBiFIFOTM WITH BUS-MATCHING
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES O. SUPPLY
VOLTAGE AND OPERATING .REE-AIR TEMPERATURE, CL = 30 p.
Commercial: Vcc=3.3V± 0.30V; for 10ns (100 MHz) operation, Vcc=3.3V ±0.15V; TA = 0°C to +70°C; JEDEC JESD8-A compliant
IDT72V3623L10(1) IDT72V3623L15
IDT72V3633L10(1) IDT72V3633L15
IDT72V3643L10(1) IDT72V3643L15
Symbol
Parameter
Min. Max. Min. Max. Unit
tA
Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35
tWFF Propagation Delay Time, CLKA↑ to FF/IR
tREF Propagation Delay Time, CLKB↑ to EF/OR
tPAE Propagation Delay Time, CLKB↑ to AE
tPAF Propagation Delay Time, CLKA↑ to AF
tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 and CLKB↑ toMBF2 LOW
or MBF1 HIGH
2
6.5
2
10
ns
2
6.5
2
8
ns
1
6.5
1
8
ns
1
6.5
1
8
ns
1
6.5
1
8
ns
0
6.5
0
8
ns
tPMR Propagation Delay Time, CLKA↑ to B0-B35(2) and CLKB↑ to A0-A35(3)
2
8
2
10
ns
tMDV Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 Valid
tRSF Propagation Delay Time, RS1 or PRS LOW to AE LOW, AF HIGH, MBF1 HIGH
and MBF2 HIGH
2
6.5
2
10
ns
1
10
1
15
ns
tEN
Enable Time, CSA and W/RA LOW to A0-A35 Active and CSB LOW and W/RB
HIGH to B0-B35 Active
2
6
2
10
ns
tDIS
Disable Time, CSA or W/RA HIGH to A0-A35 at high impedance and CSB HIGH
or W/RB LOW to B0-B35 at high impedance
1
6
1
8
ns
NOTES:
1. For 10ns speed grade only: Vcc = 3.3V +/-0.15V, TA = 0° to +70°C; JEDEC JESD8-A compliant.
2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
4. Industrial temperature range is available by special order.
9
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