IDT72V3643L15PF Просмотр технического описания (PDF) - Integrated Device Technology
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IDT72V3643L15PF
Integrated Device Technology
IDT72V3643L15PF Datasheet PDF : 28 Pages
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IDT72V3623/72V3633/72V3643 CMOS 3.3V SyncBiFIFOTM WITH BUS-MATCHING
256 x 36, 512 x 36, 1,024 x 36
TABLE 1 .LAG PROGRAMMING
SPM
FS1/SEN
FS0/SD
RS1
H
H
H
↑
H
H
L
↑
H
L
H
↑
H
L
L
↑
L
H
L
↑
L
H
H
↑
L
L
H
↑
L
L
L
↑
NOTE:
1. X register holds the offset for AE; Y register holds the offset for AF.
COMMERCIAL TEMPERATURE RANGE
X AND Y REGlSTERS(1)
64
16
8
Parallel programming via Port A
Serial Programming via SD
reserved
reserved
reserved
the third write cycle the FIFO is ready to be loaded with a data word. See Figure
5, Parallel Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values after Reset (IDT Standard and FWFT modes), for a detailed
timing diagram. The Port A data inputs used by the offset registers are (A7-A0),
(A8-A0), or (A9-A0) for the IDT72V3623, IDT72V3633 or IDT72V3643,
respectively. The highest numbered input is used as the most significant bit of
the binary number in each case. Valid programming values for the registers
range from 1 to 252 for the IDT72V3623; 1 to 508 for the IDT72V3633; and
1 to 1,020 for the IDT72V3643. After all the offset registers are programmed
from Port A, the FIFO begins normal operation.
— SERIAL LOAD
To program the X and Y registers serially, initiate a Reset with SPM LOW,
FS0/SD LOW and FS1/SEN HIGH during the LOW-to-HIGH transition of RS1.
After this reset is complete, the X and Y register values are loaded bit-wise
through the FS0/SD input on each LOW-to-HIGH transition of CLKA that the
FS1/SEN input is LOW. There are 16-, 18- or 20-bit writes needed to complete
the programming for the IDT72V3623, IDT72V3633 or the IDT72V3643,
respectively. The two registers are written in the order Y, X. Each register value
can be programmed from 1 to 252 (IDT72V3623), 1 to 508 (IDT72V3633) or
1 to 1,020 (IDT72V3643).
When the option to program the offset registers serially is chosen, the Full/
Input Ready (FF/IR) flag remains LOW until all register bits are written. FF/IR
is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit is loaded
to allow normal FIFO operation.
See Figure 6, Serial Programming of the Almost-Full Flag and Almost-
Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes).
FIFO WRITE/READ OPERATION
The state of the Port A data (A0-A35) lines is controlled by Port A Chip
Select (CSA) and Port A Write/Read select (W/RA). The A0-A35 lines are in
the High-impedance state when either CSA or W/RA is HIGH. The A0-A35
lines are active outputs when both CSA and W/RA are LOW.
Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
LOW, and FF/IR is HIGH (see Table 2). FIFO writes on Port A are independent
of any concurrent reads on Port B.
The Port B control signals are identical to those of Port A with the exception
that the Port B Write/Read select (W/RB) is the inverse of the Port A Write/Read
select (W/RA). The state of the Port B data (B0-B35) lines is controlled by the
Port B Chip Select (CSB) and Port B Write/Read select (W/RB). The B0-B35
lines are in the high-impedance state when either CSB is HIGH or W/RB is LOW.
The B0-B35 lines are active outputs when CSB is LOW and W/RB is HIGH.
Data is read from the FIFO to the B0-B35 outputs by a LOW-to-HIGH
transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is
LOW, and EF/OR is HIGH (see Table 3). FIFO reads on Port B are independent
of any concurrent writes on Port A.
The setup and hold time constraints to the port clocks for the port Chip
Selects and Write/Read selects are only for enabling write and read operations
and are not related to high-impedance control of the data outputs. If a port enable
is LOW during a clock cycle, the port’s Chip Select and Write/Read select may
change states during the setup and hold time window of the cycle.
When operating the FIFO in FWFT mode and the Output Ready flag is
LOW, the next word written is automatically sent to the FIFO’s output register by
the LOW-to-HIGH transition of the port clock that sets the Output Ready flag
HIGH. When the Output Ready flag is HIGH, data residing in the FIFO’s memory
array is clocked to the output register only when a read is selected using the
port’s Chip Select, Write/Read select, Enable, and Mailbox select.
When operating the FIFO in IDT Standard mode, regardless of whether
the Empty Flag is LOW or HIGH, data residing in the FIFO’s memory array is
clocked to the output register only when a read is selected using the port’s Chip
Select, Write/Read select, Enable, and Mailbox select. Port A Write timing
diagram can be found in Figure 7. Relevant Port B Read timing diagrams
together with Bus-Matching and Endian select can be found in Figure 8, 9 and
10.
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through at least two flip-flop
stages. This is done to improve flag-signal reliability by reducing the probability
of metastable events when CLKA and CLKB operate asynchronously to one
another. FF/IR, and AF are synchronized to CLKA. EF/OR and AE are
synchronized to CLKB. Table 4 shows the relationship of each port flag to the
number of words stored in memory.
EMPTY/OUTPUT READY FLAGS (EF/OR)
These are dual purpose flags. In the FWFT mode, the Output Ready (OR)
function is selected. When the Output-Ready flag is HIGH, new data is present
in the FIFO output register. When the Output Ready flag is LOW, the previous
data word is present in the FIFO output register and attempted FIFO reads are
ignored.
In the IDT Standard mode, the Empty Flag (EF) function is selected. When
the Empty Flag is HIGH, data is available in the FIFO’s memory for reading to
11
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