IDT72V3660L7-5BBI Просмотр технического описания (PDF) - Integrated Device Technology
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IDT72V3660L7-5BBI Datasheet PDF : 46 Pages
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3.3V HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO
1,024 x 36, 2,048 x 36
4,096 x 36, 8,192 x 36
16,384 x 36, 32,768 x 36
IDT72V3640, IDT72V3650
IDT72V3660, IDT72V3670
IDT72V3680, IDT72V3690
FEATURES:
• Choose among the following memory organizations:Commercial
IDT72V3640 1,024 x 36
IDT72V3650 2,048 x 36
IDT72V3660 4,096 x 36
IDT72V3670 8,192 x 36
IDT72V3680 16,384 x 36
IDT72V3690 32,768 x 36
• Up to 166 MHz Operation of the Clocks
• User selectable Asynchronous read and/or write ports (PBGA Only)
• User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
• Pin to Pin compatible to the higher density of IDT72V36100 and
IDT72V36110
• Big-Endian/Little-Endian user selectable byte representation
• 5V input tolerant
• Fixed, low first word latency
• Zero latency retransmit
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
• Program programmable flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• JTAG port, provided for Boundary Scan function (PBGA Only)
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• Available in a 128-pin Thin Quad Flat Pack (TQFP) or a 144-pin Plastic
Ball Grid Array (PBGA) (with additional features)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
*Available on the PBGA package only.
* WEN WCLK/WR
D0 -Dn (x36, x18 or x9)
LD SEN
*ASYW
WRITE CONTROL
LOGIC
WRITE POINTER
INPUT REGISTER
RAM ARRAY
1,024 x 36, 2,048 x 36
4,096 x 36, 8,192 x 36
16,384 x 36, 32,768 x 36
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
BE
IP
BM
IW
OW
MRS
PRS
TCK
*TRST
* TMS
* TDI
**TDO
CONTROL
LOGIC
BUS
CONFIGURATION
OUTPUT REGISTER
RESET
LOGIC
*
JTAG CONTROL
(BOUNDARY SCAN)
OE
Q0 -Qn (x36, x18 or x9)
READ
CONTROL
LOGIC
RT
RM
* ASYR
* RCLK/RD
REN
4667 drw01
IDT and the IDT logo are a registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
SEPTEMBER 2003
DSC-4667/12
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