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IDT72V3660L7-5BBI

3.3V HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

Integrated Device Technology 

IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS(1) — ASYNCHRONOUS TIMING

(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)

Commercial

Symbol

Parameter

IDT72V3640L6

IDT72V3650L6

IDT72V3660L6

IDT72V3670L6

IDT72V3680L6

IDT72V3690L6

Min.

Max.

IDT72V3640L7-5

IDT72V3650L7-5

IDT72V3660L7-5

IDT72V3670L7-5

IDT72V3680L7-5

IDT72V3690L7-5

Min.

Max. Unit

fA(4)

Cycle Frequency (Asynchronous mode)

—

100

—

83 MHz

tAA(4)

Data Access Time

0.6

8

0.6

10

ns

tCYC(4)

Cycle Time

10

—

12

—

ns

tCYH(4)

Cycle HIGH Time

4.5

—

5

—

ns

tCYL(4)

tRPE(4)

tFFA(4)

tEFA(4)

Cycle LOW Time

Read Pulse after EF HIGH

Clock to Asynchronous FF

Clock to Asynchronous EF

4.5

—

5

8

—

10

—

8

—

—

8

—

—

ns

—

ns

10

ns

10

ns

tPAFA(4) Clock to Asynchronous Programmable Almost-Full Flag

—

8

—

10

ns

tPAEA(4) Clock to Asynchronous Programmable Almost-Empty Flag

—

8

—

10

ns

NOTES:

1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

2. Pulse widths less than minimum values are not allowed.

3. Values guaranteed by design, not currently tested.

4. Paramaeters apply to the PBGA package only.

10

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