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IDT723626

CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 1,024 x 36 x 2

Integrated Device Technology 

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™

WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS

Symbol

Name

I/O

Description

A0-A35

AEA

AEB

AFA

AFC

Port A Data

I/O 36-bit bidirectional data port for side A.

PortAAlmost-Empty O Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is

Flag

less than or equal to the value in the Almost-Empty A Offset register, X2.

PortBAlmost-Empty O Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is

Flag

less than or equal to the value in the Almost-Empty B Offset register, X1.

Port A Almost-Full

Flag

O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in

FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.

Port C Almost-Full

Flag

O Programmable Almost-Full flag synchronized to CLKC. It is LOW when the number of empty locations in

FIFO2 is less than or equal to the value in the Almost-Full C Offset register, Y2.

B0-B17

BE/FWFT

Port B Data

Big-Endian/

First Word

Fall Through

Select

O 18-bit output data port for side B.

I This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation. In this

case, depending on the bus size, the most significant byte or word on Port A is read from Port B first (A-to-B

data flow) or is written to Port C first (C-to-A data flow). A LOW on BE will select Little-Endian operation.

In this case, the least significant byte or word on Port A is read from Port B first (A-to-B data flow) or is

written to Port C first (C-to-A data flow).

After Master Reset, this pin selects the timing mode. A HIGH on FWFT selects IDT Standard mode, aLOW

selects First Word Fall Through mode. Once the timing mode has been selected, the level on FWFT must

be static throughout device operation.

C0-C17 Port C Data

I 18-bit input data port for side C.

CLKA

Port A Clock

I CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or

coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH

transition of CLKA.

CLKB

Port B Clock

I CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or

coincident to CLKA. EFB/ORB and AEB are synchronized to the LOW-to-HIGH transition of CLKB.

CLKC

CSA

CSB

EFA/ORA

EFB/ORB

Port C Clock

Port A Chip Select

Port B Chip Select

Port A Empty/

Output Ready Flag

Port B Empty/

Output Ready Flag

I CLKC is a continuous clock that synchronizes all data transfers through Port C and can be asynchronous

or coincident to CLKA. FFC/IRC and AFC are synchronized to the LOW-to-HIGH transition of CLKC.

I CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35

outputs are in the high-impedance state when CSA is HIGH.

I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read data on Port B. The B0-B17

outputs are in the high-impedance state when CSB is HIGH.

O This is a dual function pin. In the IDT Standard mode, the EFA function is selected. EFA indicates whether

or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA indicates the

presence of valid data on the A0-A35 outputs, available for reading. EFA/ORA is synchronized to the

LOW-to-HIGH transition of CLKA.

O This is a dual function pin. In the IDT Standard mode, the EFB function is selected. EFB indicates whether

or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB indicates the

presence of valid data on the B0-B17 outputs, available for reading. EFB/ORB is synchronized to the

LOW-to-HIGH transition of CLKB.

ENA

FFA/IRA

Port A Enable

Port A Full/

Input Ready Flag

FFC/IRC Port C Full/

Input Ready Flag

I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.

O This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates whether

or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA

indicates whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is

synchronized to the LOW-to-HIGH transition of CLKA.

O This is a dual function pin. In the IDT Standard mode, the FFC function is selected. FFC indicates whether

or not the FIFO2 memory is full. In the FWFT mode, the IRC function is selected. IRC indicates whether or

not there is space available for writing to the FIFO2 memory. FFC/IRC is synchronized to the

LOW-to-HIGH transition of CLKC.

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