IDT723626 Просмотр технического описания (PDF) - Integrated Device Technology
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IDT723626
Integrated Device Technology
IDT723626 Datasheet PDF : 35 Pages
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IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
8 ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board
each chip buffer data between a bidirectional 36-bit bus (Port A) and two
unidirectional 18-bit buses (Port B transmits data, Port C receives data.) FIFO
data can be read out of Port B and written into Port C using either 18-bit or 9-
bit formats with a choice of Big- or Little-Endian configurations.
These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
PIN CONFIGURATION
INDEX
W/RA
1
ENA
2
CLKA
3
GND
4
A35
5
A34
6
A33
7
A32
8
Vcc
9
A31
10
A30
11
GND
12
A29
13
A28
14
A27
15
A26
16
A25
17
A24
18
A23
19
BE/FWFT
20
GND
21
A22
22
Vcc
23
A21
24
A20
25
A19
26
A18
27
GND
28
A17
29
A16
30
A15
31
A14
32
A13
33
Vcc
34
A12
35
GND
36
A11
37
A10
38
TQFP (PK128-1, order code: PF)
TOP VIEW
2
102
CLKB
101
PRS2
100
Vcc
99
C17
98
C16
97
C15
96
C14
95
GND
94
MBC
93
C13
92
C12
91
C11
90
C10
89
C9
88
C8
87
Vcc
86
C7
85
C6
84
SIZEB
83
GND
82
C5
81
C4
80
C3
79
C2
78
C1
77
C0
76
GND
75
B17
74
B16
73
SIZEC
72
Vcc
71
B15
70
B14
69
B13
68
B12
67
GND
66
B11
65
B10
3271 drw02
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