IDT723611 Просмотр технического описания (PDF) - Integrated Device Technology
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IDT723611 Datasheet PDF : 20 Pages
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IDT723611 CMOS SyncFIFO™
64 x 36
COMMERCIAL TEMPERATURE RANGES
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND
OPERATING FREE-AIR TEMPERATURES
IDT723611L15 IDT723611L20 IDT723611L30
Symbol
Parameter
Min. Max. Min. Max. Min. Max.
Unit
fS
Clock Frequency, CLKA or CLKB
– 66.7 –
50
– 33.4
Mhz
tCLK Clock Cycle Time, CLKA or CLKB
15
–
20
–
30
–
Mhz
tCLKH Pulse Duration, CLKA or CLKB HIGH
6
–
8
–
12
–
ns
tCLKL Pulse Duration, CLKA or CLKB LOW
6
–
8
–
12
–
ns
tDS
Setup Time, A0-A35 before CLKA↑ and B0-B35 4
–
5
–
6
–
ns
before CLKB↑
tENS1 CSA, W/RA, before CLKA↑; CSB, W/RB before 6
–
6
–
7
–
ns
CLKB↑
tENS2 ENA before CLKA↑; ENB before CLKB↑
4
–
5
–
6
–
ns
tENS3 MBA before CLKA↑; ENB before CLKB↑
4
–
5
–
6
–
ns
tPGS Setup Time, ODD/EVEN and PGB before
4
–
5
–
6
–
ns
CLKB↑(1)
tRSTS Setup Time, RST LOW before CLKA↑
5
–
6
–
7
–
ns
or CLKB↑(2)
tFSS
Setup Time, FS0 and FS1 before RST HIGH
5
–
6
–
7
–
ns
tDH
Hold Time, A0-A35 after CLKA↑ and B0-B35
1
–
1
–
1
–
ns
after CLKB↑
tENH1 CSA, W/RA after CLKA↑; CSB, W/RB
1
–
1
–
1
–
ns
after CLKB↑
tENH2 ENA after CLKA↑; ENB after CLKB↑
1
1
1
ns
tENH3 MBA after CLKA↑; MBB after CLKB↑
1
1
1
ns
tPGH Hold TIme, ODD/EVEN and PGB after CLKB↑(1) 0
–
0
–
0
–
ns
tRSTH Hold Time, RST LOW after CLKA↑ or CLKB↑(2)
6
–
6
–
7
–
ns
tFSH
Hold Time, FS0 and FS1 after RST HIGH
4
–
4
–
4
–
ns
tSKEW1(3) Skew Time, between CLKA↑ and CLKB↑
for EF, FF
8
–
8
–
10
–
ns
tSKEW2(3) Skew Time, between CLKA↑ and CLKB↑
for AE, AF
9
–
16
–
20
–
ns
Notes:
1. Only applies for a rising edge of CLKB that does a FIFO read.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relation-
ship between CLKA cycle and CLKB cycle.
7
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