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IDT723611

CMOS SyncFIFO 64 x 36

Integrated Device Technology 

IDT723611 CMOS SyncFIFO™

64 x 36

PIN DESCRIPTION (CONTINUED)

COMMERCIAL TEMPERATURE RANGES

Symbol

MBF2

ODD/

EVEN

PEFA

PEFB

PGA

PGB

RST

W/RA

W/RB

Name

Mail2 Register Flag

Odd/Even Parity

Select

Port-A Parity Error

Flag

Port-B Parity Error

Flag

Port-A Parity

Generation

Port-B Parity

Generation

Reset

Port-A Write/Read

Select

Port-B Write/Read

Select

I/O

Description

O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to

the mail2 register. Writes to the mail2 register are inhibited while MBF2 is

LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a port-

A read is selected and MBA is HIGH. MBF2 is set HIGH when the device is

reset.

I Odd parity is checked on each port when ODD/EVEN is HIGH, and even

parity is checked when ODD/EVEN is LOW. ODD/EVEN also selects the

type of parity generated for each port if parity generation is enabled for a read

operation.

O When any byte applied to terminals A0-A35 fails parity, PEFA is LOW.

(Port A) Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the

most significant bit of each byte serving as the parity bit. The type of parity

checked is determined by the state of the ODD/EVEN input. The parity trees

used to check the A0-A35 inputs are shared by the mail2 register to generate

parity if parity generation is selected by PGA. Therefore, if a mail2 read with

parity generation is setup by having CSA LOW, ENA HIGH, W/RA LOW, MBA

HIGH, and PGA HIGH, the PEFA flag is forced HIGH regardless of the state of

A0-A35 inputs.

O When any byte applied to terminals B0-B35 fails parity, PEFB is LOW.

(Port B) Bytes are organized as B0-B8, B9-B17, B18-B26, B27-B35, with the most

significant bit of each byte serving as the parity bit. The type of parity

checked is determined by the state of the ODD/EVEN input. The parity trees

used to check the B0-B35 inputs are shared by the mail1 register to generate

parity if parity generation is selected by PGB. Therefore, if a mail1 read with

parity generation is setup by having CSB LOW, ENB HIGH, W/RB LOW,

MBB HIGH, and PGB HIGH, the PEFB flag is forced HIGH regardless of the

state of the B0-B35 inputs

I Parity is generated for mail2 register reads from port A when PGA is HIGH.

The type of parity generated is selected by the state of the ODD/EVEN input.

Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The gener-

ated parity bits are output in the most significant bit of each byte.

I Parity is generated for data reads from port B when PGB is HIGH. The type

of parity generated is selected by the state of the ODD/EVEN input. Bytes are

organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity

bits are output in the most significant bit of each byte.

I To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-

HIGH transitions of CLKB must occur while RST is LOW. This sets the AF,

MBF1, and MBF2 flags HIGH and the EF, AE, and FF flags LOW. The LOW-

to-HIGH transition of RST latches the status of the FS1 and FS0 inputs to

select almost-full and almost-empty flag offset.

I A HIGH selects a write operation and a LOW selects a read operation on

port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the

high-impedance state when W/RA is HIGH.

I A HIGH selects a write operation and a LOW selects a read operation on

port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the

high-impedance state when W/RB is HIGH.

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