IDT723611(1999) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723611
(Rev.:1999)

CMOS SyncFIFO™ 64 x 36

Integrated Device Technology 

IDT723611

Commercial Temperature Range

CLKA

ENA

AF

tENS2

tENH2

tPAF

[64-(X+1)] Words in FIFO

tSKEW2(1)

1

(64-X) Words in FIFO

2

tPAF

CLKB

tENS2

tENH2

ENB

3024 drw 11

NOTES:

1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge

and rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKB cycle later than shown.

2. FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L).

Figure 8. Timing for AF when the FIFO is Almost-Full

CLKA

CSA

W/RA

MBA

ENA

A0 - A35

tENS1

tENS1

tENS1

tENS1

tDS

W1

tENH1

tENH1

tENH1

tENH1

tDH

CLKB

MBF1

tPMF

CSB

W/RB

tPMF

MBB

ENB

tEN

B0 - B35

NOTE:

1. Port-B parity generation off (PGB = L)

tPMR

tMDV

FIFO Output Register

tENS2

tENH2

tDIS

W1 (Remains valid in Mail1 Register after read)

Figure 9. Timing for Mail1 Register and MBF1 Flag

3024 drw 12

16

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