IDT723611(1999) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723611
(Rev.:1999)

CMOS SyncFIFO™ 64 x 36

Integrated Device Technology 

IDT723611

Commercial Temperature Range

CLKB

tCLK

tCLKH

tCLKL

EF HIGH

CSB

W/RB

MBB

ENB

B0 - B35

PGB,

ODD/

EVEN

tENS2

tENH2

tMDV

tEN

tA

Previous Data

tPGS

tPGH

tENS2

tENH2

Word 1

tPGS

tA

tPGH

Figure 4. FIFO Read Cycle Timing

tENS2

tENH2

No Operation

tDIS

Word 2

3024 drw 07

CLKA

CSA

LOW

tCLK

tCLKH tCLKL

WRA

MBA

ENA

HIGH tENS3

tENS2

tENH3

tENH2

FFA

A0 - A35

CLKB

EF

HIGH tDS

tDH

W1

tSKEW1(1)

tCLK

tCLKH tCLKL

1

Empty FIFO

2

tREF

tREF

CSB LOW

W/RB LOW

MBB LOW

tENS2

tENH2

ENB

B0 - B35

tA

W1

NOTE:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle.

and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.

3024 drw 08

If the time between the rising CLKA edge

Figure 5. EF Flag Timing and First Data Read when the FIFO is Empty

14

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