IDT7099S Просмотр технического описания (PDF) - Integrated Device Technology
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IDT7099S Datasheet PDF : 9 Pages
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IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
The IDT7099 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide very short set-up
and hold times on address, data, and all critical control inputs.
All internal registers are clocked on the rising edge of the clock
signal. An asynchronous output enable is provided to ease
asynchronous bus interfacing.
The internal write pulse width is dependent on the low to
high transitions of the clock signal allowing the shortest
possible realized cycle times. Clock enable inputs are
provided to stall the operation of the address and data input
registers without introducing clock skew for very fast inter-
leaved memory applications.
The data inputs are gated to control on-chip noise in bussed
applications. The user must guarantee that the BYTE R/W and
BIT R/W pins are low for at least one clock cycle before any
write is attempted. A High on the CE input for one clock cycle
will power down the internal circuitry to reduce static power
consumption.
The device has separate Bit Write, Byte Write, Bit Enable,
and Byte Enable pins to allow for independent control.
TRUTH TABLE I – READ/WRITE CONTROL(1)
Inputs
Synchronous(3)
Asynchronous
Outputs
CLK CE Byte R/W Bit R/W Byte OE Bit OE I/O0-7 I/O8
Mode
h
h
h
X
X High-Z High-Z Deselected, Power Down, Data I/O Disabled
h
l
h
h
h
X
X DATAIN High-Z Deselected, Power Down, Byte Data Input Enabled
l
X
X High-Z DATAIN Deselected, Power Down, Bit Data Input Enabled
h
l
l
X
X DATAIN DATAIN Deselected, Power Down, Data Input Enabled
l
l
h
X
L DATAIN DATAOUT Write Byte, Read Bit
l
l
h
X
H DATAIN High-Z Write Byte Only
l
h
l
L
X DATAOUT DATAIN Read Byte, Write Bit
l
h
l
H
X
High-Z DATAIN Write Bit Only
l
l
l
h
l
X
X DATAIN DATAIN Write Byte, Write Bit
h
L
L DATAOUT DATAOUT Read Byte, Read Bit
l
h
h
H
L
High-Z DATAOUT Read Bit Only
l
h
h
L
H DATAOUT High-Z Read Byte Only
l
h
h
H
H High-Z High-Z Data I/O Disabled
TRUTH TABLE II – CLOCK ENABLE FUNCTION TABLE(1)
3007 tbl 09
Operating Mode
Inputs
CLK(3)
CLKEN(2)
Register Inputs
ADDR
DATAIN
Register Outputs
ADDR
DATAOUT
Load "1"
l
h
h
H
H
Load "0"
l
l
l
L
L
Hold (do nothing)
h
X
X
NC
NC
X
H
X
X
NC
NC
NOTES:
3007 tbl 10
1. 'H' = High voltage level steady state, 'h' = High voltage level one set-up time prior to the low-to-high clock transition, 'L' = Low voltage level steady state
'l' = Low voltage level one set-up time prior to the Low-to-High clock transition, 'X' = Don't care, 'NC' = No change
2. CLKEN = VIL must be clocked in during Power-Up.
3. Control signals are initialted and terminated on the rising edge of the CLK, depending on their input level. When R/W and CE are low, a write cycle is initiated
on the low-to-high transition of the CLK. Termination of a write cycle is done on the next low-to-high transistion of the CLK.
6.23
8
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