IDT7099S Просмотр технического описания (PDF) - Integrated Device Technology
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IDT7099S Datasheet PDF : 9 Pages
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IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ-TO-WRITE CYCLE NO. 1, CE = VIH (2)
tCYC
tCYC
CLK
tCH
tCL
tCH
tCL
CLKEN
CE
tS
tH
W BYTE R/
W or BIT R/
ADDRESS
An
An + 1
An + 2
An + 3
DATAIN
DATAOUT
tCD
tCKLZ (3)
Dn + 2
(3)
tCKHZ
Qn
Dn + 3
3007 drw 10
TIMING WAVEFORM OF READ-TO-WRITE CYCLE NO. 2, CE = VIL(2)
tCYC
tCYC
CLK
tCH
tCL
tCH
tCL
CLKEN
CE
tS
tH
(1)
W BYTE R/
W or BIT R/
ADDRESS
An
An + 1
An + 1(1)
An + 2
DATAIN
DATAOUT
tCD
tCKLZ (3)
Dn + 1(1)
(3)
tCKHZ
Qn
Dn + 2
NOTES:
1. During dead cycle, if CE = VIL, then invalid data will be written into array. The An+1 must be rewritten on the following cycle.
2. OE low throughout.
3. Transition is measured +/-200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
3007 drw 11
6.23
7
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