IDT49FCT805BT/CT Просмотр технического описания (PDF) - Integrated Device Technology
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IDT49FCT805BT/CT Datasheet PDF : 7 Pages
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IDT49FCT805BT/CT, 806BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUIT FOR ALL OUTPUTS
VCC
7.0V
VIN
Pulse
Generator
V OUT
D.U.T.
500Ω
50pF
500Ω
RT
CL
2920 drw 07
ENABLE AND DISABLE TIME
SWITCH POSITION
Test
Switch
Disable LOW
Closed
Enable LOW
Disable HIGH
Enable HIGH
Open
DEFINITIONS:
2920 lnk 08
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
PACKAGE DELAY
INPUT
tPLH
OUTPUT
tR
tPHL
tF
3V
1.5V
0V
VOH
2.0V
1.5V
0.8V VOL
OUTPUT SKEW- tSK(o)
INPUT
OUTPUT 1
OUTPUT 2
tPLH1
tPHL1
tSK(o)
tSK(o)
tPLH2
tPHL2
3V
1.5V
0V
VOH
1.5V
VOL
VOH
1.5V
VOL
PULSE SKEW - tSK(p)
INPUT
OUTPUT
tPLH
tPHL
tSK(p) = |tPHL - tPLH|
2920 drw 08
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
2920 drw 09
3V
1.5V
0V
VOH
1.5V
VOL
PACKAGE SKEW - tSK(t)
INPUT
PACKAGE 1 OUTPUT
PACKAGE 2 OUTPUT
tPLH1
tPHL1
tSK(t)
tSK(t)
tPLH2
tPHL2
3V
1.5V
0V
VOH
1.5V
VOL
VOH
1.5V
VOL
2920 drw 10
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
t PZL
SWITCH
CLOSED
t PZH
3.5V
1.5V
t PLZ
t PHZ
0.3V
3V
1.5V
0V
3.5V
V OL
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
0.3V VOH
0V
NOTES:
2920 drw 12
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: f ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
tSK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
Package 1 and Package 2 are same device type and speed grade
2920 drw 11
9.2
6
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