ICSSSTUB32864A Просмотр технического описания (PDF) - Integrated Device Technology

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ICSSSTUB32864A

25-Bit Configurable Registered Buffer for DDR2

Integrated Device Technology 

ICSSSTUB32864A

Advance Information

DUT

Out

VDD

CL = 10 pF

(see Note 1)

RL = 50Ω

Test Point

LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT

Ou t p u t

VOH

80%

dv _f

20%

dt _f

VOL

VOLTAGE WAVEFORMS – HIGH-TO-LOW SLEW-RATE MEASUREMENT

DUT

Out

CL = 10 pF

(see Note 1)

Test Point

RL = 50Ω

LOAD CIRCUIT – LOW-TO-HIGH SLEW-RATE MEASUREMENT

dv _r

dt _r

80%

VOH

20%

Ou t put

VOL

VOLTAGE WAVEFORMS – LOW-TO-HIGH SLEW-RATE MEASUREMENT

Figure 7 — Output Slew-Rate Measurement Information (V DD = 1.8V ± 0.1V)

Notes: 1. CL includes probe and jig capacitance.

2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO =

50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).

1166—10/05/05

10

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