ICS8305AGT Просмотр технического описания (PDF) - Integrated Circuit Systems

Номер в каталоге

Компоненты Описание

Список матч

ICS8305AGT

LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS8305

LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/

LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER

TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum Typical

nCLK

IIH

Input High Current

CLK

VIN = VDD = 3.465V

VIN = VDD = 3.465V

nCLK

IIL

Input Low Current

CLK

VIN = 0V, VDD = 3.465V

V = 0V, V = 3.465V

IN

DD

-150

-5

VPP

VCMR

Peak-to-Peak Input Voltage

Common Mode Input Voltage;

NOTE 1, 2

0.15

GND + 0.5

NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.

NOTE 2: Common mode voltage is defined as VIH.

Maximum

150

150

1.3

VDD - 0.85

Units

µA

µA

µA

µA

V

V

TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

fMAX

Output Frequency

LVCMOS_CLK;

tp

LH

Propagation Delay, NOTE 1A

Low to High

CLK, nCLK;

NOTE 1B

1.75

tsk(o) Output Skew; NOTE 2, 6

Measured on the Rising Edge

350

MHz

2.75

ns

35

ps

tsk(pp) Part-to-Part Skew; NOTE 3, 6

700

ps

Buffer Additive Phase Jitter, RMS;

tjit

refer to Additive Phase Jitter Section,

NOTE 5

0.04

ps

tR / tF

odc

Output Rise/Fall Time; NOTE 4

Output Duty Cycle

20% to 80%

100

Ref = CLK/nCLK

45

Ref = LVCMOS_CLK,

ƒ ≤ 300MHz

45

700

ps

55

%

55

%

tEN

Output Enable Time; NOTE 4

5

ns

tDIS

Output Disable Time; NOTE 4

5

ns

All parameters measured at ƒ ≤ 350MHz unless noted otherwise.

NOTE 1A: Measured from the VDD/2 of the input to VDDO/2 of the output.

NOTE 1B: Measured from the differential input crossing point to VDDO/2 of the output.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at VDDO/2.

NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and

with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.

NOTE 4: These parameters are guaranteed by characterization. Not tested in production.

NOTE 5: Driving only one input clock.

NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.

8305AG

www.icst.com/products/hiperclocks.html

5

REV. B FEBRUARY 26, 2004

Share Link: