HIP6020A Просмотр технического описания (PDF) - Intersil

Номер в каталоге

Компоненты Описание

Список матч

HIP6020A

Advanced Dual PWM and Dual Linear Power Controller

Intersil 

HIP6020A

OUT2 Voltage Selection

The AGP regulator output voltage is internally set to 1.5V or

continuously on, based on the status of the SELECT pin.

SELECT pin is internally pulled ‘high’, such that left open,

the standard buck MOSFET will be continuously on, VOUT2

being equal to the input voltage (3.3V) less any voltage drop

across the MOSFET’s rDS(ON) and output inductor’s DCR.

The other setting available is 1.5V, which can be obtained by

grounding the SELECT pin using a jumper or another

suitable method capable of sinking a few tens of

microamperes. The status of the SELECT pin cannot be

changed during operation of the IC without possibly causing

a fault condition.

Application Guidelines

Soft-Start Interval

Initially, the soft-start function clamps the error amplifier’s output

of the PWM converters. This generates PHASE pulses of

increasing width that charge the output capacitor(s). After the

output voltage increases to approximately 70% of the set value,

the reference input of the error amplifier is clamped to a voltage

proportional to the SS pin voltage. The resulting output voltages

start-up as shown in Figure 3.

The soft-start function controls the output voltage rate of rise

to limit the current surge at start-up. The soft-start interval

and the surge current are programmed by the soft-start

capacitor, CSS. Programming a faster soft-start interval

increases the peak surge current. The peak surge current

occurs during the initial output voltage rise to 70% of the set

value. Using the recommended 0.1µF soft start capacitor

insures all output voltages ramp up to their set values within

10ms of the input voltages reaching POR levels.

Shutdown

Neither PWM output switches until the soft-start voltage

(VSS) exceeds the oscillator’s valley voltage. Additionally,

the reference on each linear’s amplifier is clamped to the

soft-start voltage. Holding the SS pin low (with an open drain

or open collector signal) turns off all four regulators.

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with

which the current transitions from one device to another

causes voltage spikes across the interconnecting

impedances and parasitic circuit elements. The voltage

spikes can degrade efficiency, radiate noise into the circuit,

and lead to device over-voltage stress. Careful component

layout and printed circuit design minimizes the voltage

spikes in the converter. Consider, as an example, the turn-off

transition of the upper MOSFET. Prior to turn-off, the upper

MOSFET was carrying the full load current. During the turn-

off, current stops flowing in the upper MOSFET and is picked

up by the lower MOSFET or Schottky diode. Any inductance

in the switched current path generates a large voltage spike

during the switching interval. Careful component selection,

tight layout of the critical components, and short, wide circuit

traces minimize the magnitude of voltage spikes.

There are two sets of critical components in a DC-DC

converter using a HIP6020A controller. The switching power

components are the most critical because they switch large

amounts of energy, and as such, they tend to generate

equally large amounts of noise. The critical small signal

components are those connected to sensitive nodes or

those supplying critical bypass current.

The power components and the controller IC should be

placed first. Locate the input capacitors, especially the high-

frequency ceramic de-coupling capacitors, close to the

power switches. Locate the output inductor and output

capacitors between the MOSFETs and the load. Locate the

PWM controller close to the MOSFETs.

The critical small signal components include the bypass

capacitor for VCC and the soft-start capacitor, CSS. Locate

these components close to their connecting pins on the

control IC. Minimize any leakage current paths from SS

node, since the internal current source is only 28µA.

A multi-layer printed circuit board is recommended. Figure 7

shows the connections of the critical components in the

converter. Note that the capacitors CIN and COUT each

could represent numerous physical capacitors. Dedicate one

solid layer for a ground plane and make all critical

component ground connections with vias to this layer.

Dedicate another solid layer as a power plane and break this

plane into smaller islands of common voltage levels. The

power plane should support the input power and output

power nodes. Use copper filled polygons on the top and

bottom circuit layers for the PHASE nodes, but do not

unnecessarily oversize these particular islands. Since the

PHASE nodes are subjected to very high dV/dt voltages, the

stray capacitor formed between these islands and the

surrounding circuitry will tend to couple switching noise. Use

the remaining printed circuit layers for small signal wiring.

The wiring traces from the control IC to the MOSFET gate

and source should be sized to carry 2A peak currents.

10

Share Link: