HFA3861A Просмотр технического описания (PDF) - Intersil

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HFA3861A

Direct Sequence Spread Spectrum Baseband Processor

Intersil 

HFA3861A

decoded and descrambled before being sent to the header

detection section.

In the 1Mbps DBPSK mode, data demodulation is performed

the same as in header processing. In the 2Mbps DQPSK

mode, the demodulator demodulates two bits per symbol

and differentially decodes these bit pairs. The bits are then

serialized and descrambled prior to being sent to the output.

In the CCK modes, the receiver removes carrier frequency

offsets and uses a bank of correlators to detect the

modulation. A biggest picker finds the largest correlation in

the I and Q Channels and determines the sign of those

correlations. For this to happen, the demodulator must know

the starting phase which is determined by referencing the

data to the last bit of the header. Each symbol demodulated

determines 1 or 2 nibbles of data. This is then serialized and

descrambled before being passed to the output.

Chip tracking in the CCK modes is chip decision directed.

Carrier tracking is via a lead/lag filter using a digital Costas

phase detector.

Acquisition Description

A projected worst case time line for the acquisition of a

signal with a short preamble and header is shown. The

synchronization part of the preamble is 56 symbols long

followed by a 16-bit SFD. The receiver must monitor the

antenna to determine if a signal is present. The timeline is

broken into 10µs blocks (dwells) for the scanning process.

This length of time is necessary to allow enough integration

of the signal to make a good acquisition decision. This worst

case time line example assumes that the signal arrives part

way into the first dwell such as to just barely catch detection.

The signal and the scanning process are asynchronous and

the signal could start anywhere. In this timeline, it is

assumed that the signal is present in the first 10µs dwell, but

was missed due to power amplifier ramp up.

Meanwhile signal quality and signal frequency

measurements are made simultaneous with symbol timing

measurements. A CS1 followed by SQ1 active, or two

consecutive SQ1’s will cause the part to exit the acquisition

phase and enter the tracking phase.

Prior to initial acquisition the NCO was inactive and DPSK

demodulation processing was used. Carrier phase

measurement are done on a symbol by symbol basis

afterward and coherent DPSK demodulation is in effect.

After a brief setup time as illustrated on the timeline of, the

signal begins to emerge from the demodulator.

It takes 7 more symbols to seed the descrambler before

valid data is available. This occurs in time for the SFD to be

received. At this time the demodulator is tracking and in the

coherent PSK demodulation mode it will no longer

acquire signals.

TX

POWER

RAMP

2

20 SYMBOLS

AGC SETTLE AND LOCK

AND INITIAL DETECTION

56 SYMBOL SYNC

20 SYMBOLS

7 SYM

VERIFY AND CIR/FREQUENCY

ESTIMATION AND CMF/NCO

JAMMING

SEED

DESCRAMBLER

START SFD DETECTION

FIGURE 10. ACQUISITION TIMELINE

SFD

16 SYMBOLS

SFD DET

START DATA

15

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