HD6433044F Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics
Номер в каталоге
Компоненты Описание
Список матч
HD6433044F Datasheet PDF : 867 Pages
| |||
10.2.9 Buffer Registers (BRA, BRB) ........................................................................ 321
10.2.10 Timer Control Registers (TCR) ...................................................................... 322
10.2.11 Timer I/O Control Register (TIOR)................................................................ 324
10.2.12 Timer Status Register (TSR)........................................................................... 326
10.2.13 Timer Interrupt Enable Register (TIER)......................................................... 329
10.3 CPU Interface ................................................................................................................. 331
10.3.1 16-Bit Accessible Registers ............................................................................ 331
10.3.2 8-Bit Accessible Registers .............................................................................. 333
10.4 Operation ........................................................................................................................ 335
10.4.1 Overview......................................................................................................... 335
10.4.2 Basic Functions............................................................................................... 336
10.4.3 Synchronization .............................................................................................. 346
10.4.4 PWM Mode .................................................................................................... 348
10.4.5 Reset-Synchronized PWM Mode ................................................................... 352
10.4.6 Complementary PWM Mode.......................................................................... 355
10.4.7 Phase Counting Mode..................................................................................... 365
10.4.8 Buffering......................................................................................................... 367
10.4.9 ITU Output Timing......................................................................................... 374
10.5 Interrupts......................................................................................................................... 376
10.5.1 Setting of Status Flags .................................................................................... 376
10.5.2 Clearing of Status Flags.................................................................................. 378
10.5.3 Interrupt Sources and DMA Controller Activation ........................................ 379
10.6 Usage Notes .................................................................................................................... 380
Section 11 Programmable Timing Pattern Controller ......................................... 395
11.1 Overview......................................................................................................................... 395
11.1.1 Features........................................................................................................... 395
11.1.2 Block Diagram................................................................................................ 396
11.1.3 TPC Pins ......................................................................................................... 397
11.1.4 Registers ......................................................................................................... 398
11.2 Register Descriptions...................................................................................................... 399
11.2.1 Port A Data Direction Register (PADDR) ...................................................... 399
11.2.2 Port A Data Register (PADR) ......................................................................... 399
11.2.3 Port B Data Direction Register (PBDDR) ...................................................... 400
11.2.4 Port B Data Register (PBDR) ......................................................................... 400
11.2.5 Next Data Register A (NDRA)....................................................................... 401
11.2.6 Next Data Register B (NDRB) ....................................................................... 403
11.2.7 Next Data Enable Register A (NDERA) ........................................................ 405
11.2.8 Next Data Enable Register B (NDERB)......................................................... 406
11.2.9 TPC Output Control Register (TPCR)............................................................ 407
11.2.10 TPC Output Mode Register (TPMR).............................................................. 410
Share Link: 