HD6433044F Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

Номер в каталоге

Компоненты Описание

Список матч

HD6433044F

Hitachi Single-Chip Microcomputer

Hitachi -> Renesas Electronics 

5.1.3 Pin Configuration............................................................................................ 83

5.1.4 Register Configuration.................................................................................... 83

5.2 Register Descriptions...................................................................................................... 84

5.2.1 System Control Register (SYSCR)................................................................. 84

5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ....................................... 85

5.2.3 IRQ Status Register (ISR) .............................................................................. 92

5.2.4 IRQ Enable Register (IER) ............................................................................. 93

5.2.5 IRQ Sense Control Register (ISCR) ............................................................... 94

5.3 Interrupt Sources............................................................................................................. 95

5.3.1 External Interrupts .......................................................................................... 95

5.3.2 Internal Interrupts ........................................................................................... 96

5.3.3 Interrupt Vector Table ..................................................................................... 96

5.4 Interrupt Operation ......................................................................................................... 100

5.4.1 Interrupt Handling Process ............................................................................. 100

5.4.2 Interrupt Sequence .......................................................................................... 105

5.4.3 Interrupt Response Time................................................................................. 106

5.5 Usage Notes .................................................................................................................... 107

5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction ................ 107

5.5.2 Instructions that Inhibit Interrupts .................................................................. 108

5.5.3 Interrupts during EEPMOV Instruction Execution......................................... 108

5.5.4 Notes on External Interrup to during Use....................................................... 108

Section 6 Bus Controller............................................................................................ 111

6.1 Overview......................................................................................................................... 111

6.1.1 Features........................................................................................................... 111

6.1.2 Block Diagram................................................................................................ 112

6.1.3 Input/Output Pins............................................................................................ 113

6.1.4 Register Configuration.................................................................................... 113

6.2 Register Descriptions...................................................................................................... 114

6.2.1 Bus Width Control Register (ABWCR) ......................................................... 114

6.2.2 Access State Control Register (ASTCR) ........................................................ 115

6.2.3 Wait Control Register (WCR)......................................................................... 116

6.2.4 Wait State Controller Enable Register (WCER)............................................. 117

6.2.5 Bus Release Control Register (BRCR)........................................................... 118

6.2.6 Chip Select Control Register (CSCR) ............................................................ 119

6.3 Operation ........................................................................................................................ 121

6.3.1 Area Division.................................................................................................. 121

6.3.2 Chip Select Signals ......................................................................................... 123

6.3.3 Data Bus.......................................................................................................... 124

6.3.4 Bus Control Signal Timing ............................................................................. 125

6.3.5 Wait Modes ..................................................................................................... 133

Share Link: