GS9062(2005) Просмотр технического описания (PDF) - Gennum -> Semtech
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GS9062 Datasheet PDF : 46 Pages
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Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
33, 68
CORE_GND
–
34
F
Synchronous
with PCLK
35
V
Synchronous
with PCLK
36
H
Synchronous
with PCLK
37, 64
CORE_VDD
–
Type
Power
Input
Input
Input
Power
GS9062 Data Sheet
Description
Ground connection for the digital core logic. Connect to digital
GND.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the ODD / EVEN field of the video signal when
DETECT_TRS is set LOW. The device will set the F bit in all
outgoing TRS signals for the entire period that the F input signal
is HIGH (IOPROC_EN/DIS must also be HIGH).
The F signal should be set HIGH for the entire period of field 2
and should be set LOW for all lines in field 1 and for all lines in
progressive scan systems.
The F signal is ignored when DETECT_TRS = HIGH.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video field / frame that is used
for vertical blanking when DETECT_TRS is set LOW. The device
will set the V bit in all outgoing TRS signals for the entire period
that the V input signal is HIGH (IOPROC_EN/DIS must also be
HIGH).
The V signal should be set HIGH for the entire vertical blanking
period and should be set LOW for all lines outside of the vertical
blanking interval.
The V signal is ignored when DETECT_TRS = HIGH.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video line containing active
video data when DETECT_TRS is set LOW. The device will set
the H bit in all outgoing TRS signals for the entire period that the
H input signal is HIGH (IOPROC_EN/DIS must also be HIGH).
H signal timing is configurable via the H_CONFIG bit of the
IOPROC_DISABLE register, accessible via the host interface.
Active Line Blanking (H_CONFIG = 0h)
The H signal should be set HIGH for the entire horizontal
blanking period, including the EAV and SAV TRS words, and
LOW otherwise. This is the default setting.
TRS Based Blanking (H_CONFIG = 1h)
The H signal should be set HIGH for the entire horizontal
blanking period as indicated by the H bit in the received TRS ID
words, and LOW otherwise.
Power supply connection for the digital core logic. Connect to
+1.8V DC digital.
22209 - 5 May 2005
9 of 46
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