GS9062(2005) Просмотр технического описания (PDF) - Gennum -> Semtech
Номер в каталоге
Компоненты Описание
Список матч
GS9062 Datasheet PDF : 46 Pages
| |||
GS9062 Data Sheet
1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Number
Name
1
CP_VDD
Timing
–
2
PD_GND
–
3
PD_VDD
–
4, 6 – 8,
10 – 11,
14 – 17, 31,
70 – 71
5
9
NC
–
RSV
DVB_ASI
–
Non
Synchronous
12
20bit/10bit
Non
Synchronous
13
IOPROC_EN/DIS
Non
Synchronous
Type
Power
Power
Power
–
–
Input
Input
Input
Description
Power supply connection for the charge pump. Connect to +3.3V
DC analog.
Ground connection for the phase detector. Connect to analog
GND.
Power supply connection for the phase detector. Connect to
+1.8V DC analog.
No connect.
Reserved – connect to analog ground.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When set HIGH in conjunction with SMPTE_BYPASS = LOW,
the device will be configured to operate in DVB-ASI mode.
When set LOW, the device will not support the encoding of
received DVB-ASI data.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select the input data bus width in SMPTE or
Data-Through modes. This signal is ignored in DVB-ASI mode.
When set HIGH, the parallel input will be 20-bit demultiplexed
data.
When set LOW, the parallel input will be 10-bit multiplexed data.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable I/O processing features.
When set HIGH, the following I/O processing features of the
device are enabled:
• EDH Packet Generation and Insertion
• SMPTE 352M Packet Generation and Insertion
• ANC Data Checksum Calculation and Insertion
• TRS Generation and Insertion
• Illegal Code Remapping
To enable a subset of these features, keep IOPROC_EN/DIS
HIGH and disable the individual feature(s) in the
IOPROC_DISABLE register accessible via the host interface.
When set LOW, the I/O processing features of the device are
disabled, regardless of whether the features are enabled in the
IOPROC_DISABLE register.
22209 - 5 May 2005
6 of 46
Share Link: 