GL811E Просмотр технического описания (PDF) - GENESYS LOGIC

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GL811E

USB 2.0 to ATA / ATAPI Bridge Controller

GENESYS LOGIC 

GL811E USB 2.0 to ATA/ATAPI Bridge Controller

Note:

The host shall not assert DMACK_ or negate both CS0_ and CS1_ until the assertion of DMARQ is detected.

The maximum time from the assertion of DMARQ to the assertion of DMACK_ or the negation of both CS0_

and CS1_ is not defined.

Figure 6.1 - Initiating a Multiword DMA Data Burst

©2000-2006 Genesys Logic Inc. - All rights reserved.

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