GL811E Просмотр технического описания (PDF) - GENESYS LOGIC

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GL811E

USB 2.0 to ATA / ATAPI Bridge Controller

GENESYS LOGIC 

GL811E USB 2.0 to ATA/ATAPI Bridge Controller

Register transfer timing parameters

t0 Cycle time

t1 Address valid to DIOR_/ DIOW_ setup

t2 DIOR_/ DIOW_ pulse width 8-bit

t2i DIOR_/ DIOW_ recovery time

t3 DIOW_ data setup

t4 DIOW_ data hold

t5 DIOR_ data setup

t6 DIOR_ data hold

t6Z DIOR_ data tristate

t9 DIOR_/ DIOW_ to address valid hold

tRD

Read Data Valid to IORDY active

(if IORDY initially low after tA)

tA IORDY Setup time

tB IORDY Pulse Width

tC IORDY assertion to release (max)

6.4.2 Multiword DMA data transfer

Register transfer timing parameters

t0 Cycle time

tD DIOR_/ DIOW_ asserted pulse width

tE DIOR_ data access

tF DIOR_ data hold

tG DIOR_/ DIOW_ data setup

tH DIOW_ data hold

tI DMACK to DIOR_/ DIOW_ setup

tJ DIOR_/ DIOW_ to DMACK hold

tKR DIOR_ negated pulse width

tKW DIOW_ negated pulse width

tLR DIOR_ to DMARQ delay

tLW DIOW_ to DMARQ delay

tM CS(1:0) (max) valid to DIOR_/ DIOW_

tN CS(1:0) hold

tZ DMACK_ to read data released

Timing (ns)

2000

1000

300

900

80

40

-

-

-

900

-

-

-

Timing (ns)

120

80

-

-

40

18

18

20

36

36

-

-

36

18

-

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