GL800HT25 Просмотр технического описания (PDF) - GENESYS LOGIC

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GL800HT25

USB 2.0 UTMI Compliant Transceiver IP Core

GENESYS LOGIC 

GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core

3.2 Block Diagram

Data+

Data-

HS XCVR

Rcv

Status/

Control

Xmit

FS XCVR

Rcv

Status/

Control

Xmit

HS

Elasticity

DLL

Buffer

FS DLL

& Data

Recovery

NRZI

Bit

M

Decoder

Unstuffer

U

X

Receive

State

Machine

Rx

Register

Parallel

Rx Data

Transmit

State

Machine

NRZI

Encoder

Tx

Register

Bit

Stuffer

Parallel

Tx Data

Analog Front End

External

Crystal

Clock

Multiplier

CLK

Control

Control

Logic

Figure 3.2 - Block Diagram

1. HS XCVR

HS XCVR contains the low-level analog circuitry required to physically interface USB 2.0 signaling to the

USB DP/DM signal lines.

2. FS XCVR

FS XCVR includes the logic necessary to send and receive the FS data on USB.

3. Clock Multiplier

Clock Multiplier generates the internal clocks for the GL800HT25 USB 2.0 Transceiver and the CLK30

signal. All data transfer signals are synchronized with the CLK30 signal.

In HS mode there is one clock cycle per byte time. The frequency of clock does not change when the UTMI

is switched between HS to FS modes. In FS mode there are 5 clock cycles per FS bit time, typically 40

clock cycles per FS byte time. If a received byte contains a stuffed bit then the byte boundary can be

stretched to 45 clock cycles, and two stuffed bits would result in a 50 clock delay between bytes.

4. HS DLL (High Speed Delay Line PLL)

DLL extracts clock and data from the data received over the USB 2.0 interface for reception by the Receive

Deserializer. The data output from the DLL is synchronous with the local clock.

©2000-2003 Genesys Logic Inc.—All rights reserved.

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