GL800HT25 Просмотр технического описания (PDF) - GENESYS LOGIC

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GL800HT25

USB 2.0 UTMI Compliant Transceiver IP Core

GENESYS LOGIC 

GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core

TABLE OF CONTENTS

CHAPTER 1 GENERAL DESCRIPTION........................................................................ 6

CHAPTER 2 FEATURES ................................................................................................... 7

CHAPTER 3 BLOCK DIAGRAM..................................................................................... 8

3.1 SYSTEM CONFIGURATION.............................................................................................. 8

3.2 BLOCK DIAGRAM........................................................................................................... 9

CHAPTER 4 PIN ASSIGNMENT.................................................................................... 11

4.1 PINOUTS ....................................................................................................................... 11

4.2 PIN LIST........................................................................................................................ 12

4.3 PIN DESCRIPTIONS ....................................................................................................... 12

CHAPTER 5 FUNCTIONAL DESCRIPTION............................................................... 15

5.1 TRANSMIT OPERATION................................................................................................ 15

5.1.1 Transmit State Diagram..................................................................................... 15

5.1.2 Transmit Timing for Data Packet ..................................................................... 16

5.2 RECEIVE OPERATION .................................................................................................. 16

5.2.1 Receive State Diagram ....................................................................................... 16

5.2.2 Receive Timing for Data Packet (with CRC-16).............................................. 17

5.3 TIMING CHART ............................................................................................................ 18

5.3.1 CLK30 Rising and Falling Edge VS. Input/Output Signals ........................... 18

5.3.2 Relationship Between Mode Change and Other Input Signals ...................... 19

CHAPTER 6 PACKAGE DIMENSION.......................................................................... 20

©2000-2003 Genesys Logic Inc.—All rights reserved.

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