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HM514100DS-7 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HM514100DS-7
Hitachi
Hitachi -> Renesas Electronics Hitachi
HM514100DS-7 Datasheet PDF : 26 Pages
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HM514100D Series
4,194,304-word × 1-bit Dynamic RAM
ADE-203-680 (Z)
Preliminary
Rev. 0.0
Dec. 3, 1996
Description
The Hitachi HM514100D is a CMOS dynamic RAM organized 4,194,304 word × 1-bit. HM514100D has
realized higher density, higher performance and various functions by employing 0.8 µm CMOS process
technology and some new CMOS circuit design technologies. The HM514100D offers Fast Page Mode
as a high speed access mode. Multiplexed address input permits the HM514100D to be packaged in standard
300-mil 26-pin plastic SOJ and 26-pin plastic TSOP II.
Features
Single 5 V (±10%)
High speed
Access time : 60 ns/70 ns/80 ns (max)
Low power dissipation
Active mode : 605 mW/550 mW/495 mW (max)
Standby mode : 11 mW (max)
0.55 mW (max) (L-version)
Fast page mode capability
1024 refresh cycles : 16 ms
: 128 ms (L-version)
3 variations of refresh
RAS-only refresh
CAS-before-RAS refresh
Hidden refresh
Test function
Battery backup operation (L-version)
Preliminary: This document contains information on a new product. Specifications and information
contained herein are subject to change without notice.

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