EM564081 Просмотр технического описания (PDF) - Etron Technology

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EM564081

512K x 8 Low Power SRAM

Etron Technology 

EtronTech

Write Cycle 3

(CE2 Controlled)(See Note 4)

Address

tAS

WE#

CE1#

tWC

tWP

tCW

EM564081

tWR

CE2

DOUT

DIN

tCW

tWHZ

tLZ

(See Note 5)

tDS

tDH

VALID DATA IN

Note:

1. WE# remains HIGH for the read cycle.

2. If CE1# goes LOW (or CE2 goes HIGH) with or after WE# goes LOW, the outputs will remain at high

impedance.

3. If CE1# goes HIGH (or CE2 goes LOW) coincident with or before WE# goes HIGH, the outputs will remain

at high impedance.

4. If OE# is HIGH during the write cycle, the outputs will remain at high impedance.

5. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be

applied.

Preliminary

9

Rev 0.7

January 2001

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