DS2422 Просмотр технического описания (PDF) - Maxim Integrated

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DS2422

1-Wire Temperature/Datalogger with 8KB Datalog Memory

Maxim Integrated 

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DS2422

System Requirement

Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The

specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily

loaded systems, an active pullup such as that found in the DS2480B may be required.

Capacitance on the data pin could be 800pF when VPUP is first applied. If a 2.2k resistor is used to pull up the data line, 2.5µs

after VPUP has been applied the parasite capacitance will not affect normal communications.

Guaranteed by design, not production tested.

VTL and VTH are functions of the internal supply voltage, which is a function of VPUP and the 1-Wire recovery times. The VTH and

VTL maximum specifications are valid at VPUP = 5.25V. In any case, VTL < VTH < VPUP.

Voltage below which, during a falling edge on I/O, a logic '0' is detected.

The voltage on I/O needs to be less or equal to VILMAX whenever the master drives the line low.

Voltage above which, during a rising edge on I/O, a logic '1' is detected.

After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by VHY to be detected as logic '0'.

The I-V characteristic is linear for voltages less than 1V.

The earliest recognition of a negative edge is possible at tREH after VTH has been previously reached.

Highlighted numbers are NOT in compliance with the published iButton standards. See comparison table below.

Interval during the negative edge on I/O at the beginning of a Presence Detect pulse between the time at which the voltage is

90% of VPUP and the time at which the voltage is 10% of VPUP.

 in Figure 16 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to VTH. The actual

maximum duration for the master to pull the line low is tW1LMAX + tF -  and tW0LMAX + tF -  respectively.

 in Figure 16 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to the input high threshold

of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.

This is the expected range when using a crystal equivalent to the Seiko SPT2AF-12.5PF20PPM ..

Time to reach 63% of the temperature change; measured at a temperature transition step from +25°C to +85°C.

A 2-point calibration trim at 3V must be done to achieve the specified accuracy at 3V. See Application Note 2810, DS2422 Trim

Procedure and Software Correction, for details.

The duration is user-programmable from 0ms (code 00h) to 127.5ms (code FFh) with a tolerance of ±0.5ms. See Delay Register,

address 400h, for details.

Guaranteed by design, not production tested to -40°C.

STANDARD VALUES

DS2422 VALUES

PARAMETER

STANDARD SPEED OVERDRIVE SPEED STANDARD SPEED OVERDRIVE SPEED

NAME

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

tSLOT (incl. tREC)

61µs

(undef.) 7µs

(undef.)

65µs1)

(undef.) 9.5µs

(undef.)

tRSTL

480µs

(undef.) 48µs

80µs

690µs

720µs

70µs

80µs

tPDH

15µs

60µs

2µs

6µs

15µs

63.5µs

2µs

7µs

tPDL

60µs

240µs

8µs

24µs

60µs

287µs

7µs

28µs

tW0L

60µs

120µs

6µs

16µs

60µs

120µs

1) Intentional change, longer recovery time requirement due to modified 1-Wire front end.

7.5µs

12µs

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