DS2422 Просмотр технического описания (PDF) - Maxim Integrated
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DS2422 Datasheet PDF : 49 Pages
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DS2422
MEMORY
The memory map of the DS2422 is shown in Figure 7. The 512 bytes general-purpose SRAM are located in pages
0 through 15. The various registers to set up and control the device fill page 16 and 17, called Register Pages 1
and 2 (details in Figure 8). Pages 18 and 19 provide storage space for calibration data. They can alternatively be
used as extension of the general-purpose memory. The Trim Register Page holds registers that are used to tune
the timing of the serial data interface and to trim the on-chip temperature converter. The "datalog" logging memory
starts at address 1000h (page 128) and extends over 256 pages. The memory pages 20 to 31 and 33 to 127 are
reserved for future extensions. The scratchpad is an additional page that acts as a buffer when writing to the SRAM
memory or the register page. The data- and calibration memory can be written at any time. The access type for the
two register pages and the Trim Register Page is register-specific and depends on whether the device is pro-
grammed for a mission. Figures 8A and 8B show the details. The datalog memory is read-only for the user. It is
written solely under supervision of the on-chip control logic. Due to the special behavior of the write access logic
(write scratchpad, copy scratchpad) it is recommended to only write full pages at a time. This also applies to all the
register pages and the calibration memory. See section Address Register and Transfer Status for details.
Figure 8A. DS2422 Register Pages Map
ADDR
b7
b6
b5
b4
b3
b2
b1
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0
0
0
0
CENT
0
0
1
0
1
BOR
1
0
0
0
0
CENT
10 Seconds
Single Seconds
10 Minutes
Single Minutes
12/24
20h.
AM/PM
10h.
Single Hours
0
10 Date
Single Date
0
0
10m.
Single Months
10 Years
Single Years
Low Byte
0
High Byte
Low Threshold
High Threshold
Low Threshold
High Threshold
Low Byte
0
0
0
0
High Byte
Low Byte
High Byte
0
0
0
0
0
ETHA
1
1
1
1
1
EDHA
0
0
0
0
0
EHSS
1
SUTA
RO
DLFS TLFS
EDL
1
1
1
DHF
DLF
THF
1
0
WFTA MEMC
0
MIP
LR
Low Byte
Center Byte
High Byte
10 Seconds
Single Seconds
10 Minutes
Single Minutes
12/24
20h.
AM/PM
10h.
Single Hours
0
10 Date
Single Date
0
0
10m.
Single Months
10 Years
Single Years
(no function; reads 00h)
Low Byte
Center Byte
High Byte
Low Byte
Center Byte
High Byte
Configuration Code
EPW
b0
Function
Real-
Time Clock
Registers
0
ETLA
EDLA
EOSC
ETL
TLF
0
Sample
Rate
Temp.
Alarms
Data
Alarms
Latest
Temp.
Latest
Data
T.Alm.En.
D.Alm.En.
RTC En.
Mis. Cntrl.
Alm. Stat.
Gen. Stat.
Start
Delay
Counter
Mission
Time
Stamp
(N/A)
Mission
Samples
Counter
Device
Samples
Counter
Flavor
PW. Cntrl.
Access*
R/W; R
R/W; R
R/W; R
R/W; R
R; R
R; R
R/W; R
R/W; R
R/W; R
R/W; R
R; R
R; R
R/W; R
R; R
R; R
R; R
R; R
R; R
R/W; R
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