CY7C9235A Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C9235A Datasheet PDF : 8 Pages
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CY7C9235A
CY7C9235A Description
Input Register
The input register is clocked by the rising edge of CKW. This
register captures the data present at the PD0−9 inputs on every
clock cycle. In addition to the data inputs, all control inputs
except OE are also captured at each rising edge of CKW. This
includes BYPASS, DVB_EN, SVS_EN, SC/D_EN, TRS_DET,
TRS_FILT, ENN, and ENA.
TRS Filter
The TRS Filter is used to convert all 8-bit TRS characters
(000–003 and 3FC–3FF in 10-bit hex) to their full 10-bit value.
If TRS_FILT is active (LOW) and any of these values are
detected in the input register, the lower two bits are forced to
either zeros or ones respectively. This allows the encoder to
be used with both 8- and 10-bit SMPTE character streams.
If TRS_FILT is HIGH, the filter function is disabled and all
characters are passed from the input register to the SMPTE
scrambler unmodified.
TRS Detector
When operated in SMPTE mode (DVB_EN is HIGH), the TRS
detector looks for the most significant eight bits of the input
register to be either all ones or all zeros. If either of these
values are detected, the TRS_DET output will go LOW
following the rising edge of CKW, and remain LOW until a
character is detected in the input register that is not all zeros
or ones, or DVB_EN is latched LOW.
SMPTE Scrambler
The SMPTE scrambler implements a parallel encoded version
of a linear-feedback shift register. It encodes the data present
in the input register using the ×9 + ×4 + 1 polynomial to
increase the transition density of the serial data stream and to
decrease the DC-content of the transmitted serial bit stream.
NRZI Encoder
The scrambled data is also fed through an NRZ-to-NRZI
encoder. This also increases the transition density of the serial
data stream, decreases the DC-content of the transmitted
serial bit stream, and makes the serial stream insensitive to
polarity inversions.
DVB-ASI Operation
The CY7C9235A is designed to operate in both SMPTE-259M
and DVB-ASI environments. When operated in SMPTE-only
environments, the DVB control inputs may be tied to either
VCC or VSS as needed to place them in a known state. When
not used for DVB operation, the ENA, ENN, SVS_EN, and
SC/D_EN inputs many be tied to either VCC or VSS. DVB_EN
must be tied or driven HIGH.
DVB-ASI operation is enabled by asserting DVB_EN LOW.
This signal is latched by the rising edge of the CKW clock.
When the CY7C9235A is placed in DVB mode, the SMPTE
and NRZI encoders are bypassed, and the data latched into
the input register is routed directly to the output register.
Error Propagation
For those DVB-ASI implementations that do not require propa-
gation of detected errors, the Q9 output may be forced to a
zero by setting SVS_EN LOW. When SVS_EN is HIGH (and
the encoder is in DVB mode) the PD9 data latched into the
input register is routed to the output register and to the
CY7B9234 SVS input.
Command Code Generation
The DVB-ASI interface does not normally transmit any
command characters other than the K28.5 code that is used
both for synchronization and as a fill character when data is
not being transmitted. These K28.5 characters may be
generated by two methods; by controlling when the
CY7C9235A is enabled using the ENA and ENN inputs, or by
placing a C5.0 character on the PD9–0 inputs when one of the
two enables is active.
If the generation of K28.5 fill characters is to be controlled
using the ENA or ENN inputs, the SC/D_EN input should be
driven LOW or connected to VSS. This will insure that the PD0
data bit is not routed to the output register by forcing the Q0
output to always be LOW.
If the generation of a K28.5 characters is controlled by trans-
mission of a C5.0 character, the SC/D_EN input must be HIGH
to allow the PD0 input to be propagated to the Q0 output.
Document #: 38-02082 Rev. **
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