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CY7C9235A

SMPTE-259M/DVB-ASI Scrambler/Controller

Cypress Semiconductor 

CY7C9235A

Pin Descriptions CY7C9235A SMPTE-259M Encoder (continued)

Name

I/O

SC/D_EN Input

PD9(SVS) Input

PD8–1

Input

PD0(SC/D) Input

Q9(SVS) Output

Q8–1

Output

Q0(SC/D) Output

DVB_EN Input

CKW

Input

ENA_OUT Output

OE

Input

VCC

VSS

Description

Special Character/Data Select Enable. This input is only valid when DVB_EN is active (LOW). If

SC/D_EN is HIGH and a HIGH input is present on PD0, Q0 will also be high on a following clock

cycle, forcing the CY7B9234 serializer to generate an 8B/10B control character as selected by the

character present on the PD8–1 inputs. If SC/D_EN is LOW, the level present on PD0 is ignored and

Q0 is forced to a LOW (data only) state.

Parallel Data 9 or Send Violation Symbol. This is the MSB of the input data field. It is latched in

the input register at the rising edge of CKW. When DVB_EN is active (LOW) and SVS_EN is HIGH,

this latched input is routed to the output register bit Q9 (SVS). When DVB_EN is active (LOW) and

SVS_EN is LOW, output register bit Q9 (SVS) is forced to a LOW (zero) level. When DVB_EN is

inactive (HIGH), this latched input is routed to the scrambler and NRZI encoder.

Parallel Data 8 through 1. The signals present at the PD8–1 inputs are latched in the input register

at the rising edge of CKW. When DVB_EN is HIGH, these signals are the middle eight bits of the

SMPTE 10-bit data field, and are then routed to the scrambler and NRZI encoder. When DVB_EN

is active (LOW), these signals are full DVB-ASI data bus, and are then routed to the Q8−1 outputs.

Parallel Data 0 or Special Code/Data Select. This is the LSB of the input data field. It is latched in

the input register at the rising edge of CKW. When DVB_EN is active (LOW) and SC/D_EN is HIGH,

this input is routed to output register bit Q0 (SVS). When DVB_EN is active (LOW) and SC/D_EN is

LOW, output register bit Q0 (SC/D) is forced to a LOW (zero) level. When DVB_EN is inactive (HIGH),

this input data bit is routed through the input register and the scrambler and NRZI encoder.

Output Bit 9. This is the MSB of the output register. It should be connected directly to the CY7B9234

serializer input signal SVS(Dj).

Output Bits 8 through 1. These signals should be connected directly to the CY7B9234 serializer

input signals D7−0 respectively.

Output Bit 0. This is the LSB of the output register. It should be connected directly to the CY7B9234

serializer input signal SC/D(Da).

DVB Mode Enable. This signal is sampled by the rising edge of the CKW clock. If DVB_EN is active

(LOW), the data present on the PD0−9, ENA, and ENN inputs are latched and routed to the Q0−9 and

ENA_OUT outputs.

Clock Write. This clock controls all synchronous operations of the CY7C9235A. It operates at the

character rate which is equivalent to one tenth the serialized bit-rate. This clock also connects directly

to the CKW input of the CY7B9234 serializer.

Enable Parallel Data Out. This output attached directly to the CY7B9234 ENA input, and identifies

when valid data is available at the CY7C9235A outputs. If used only for SMPTE-259M data streams,

this output may be left open, with the ENA input to the CY7B9234 directly connected to VSS.

Output Enable. When this signal is HIGH all outputs are driven to their normal logic levels. When

LOW, all outputs are placed in a High-Z state.

Power.

Ground.

Document #: 38-02082 Rev. **

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