MCM62486BFN11 Просмотр технического описания (PDF) - Motorola => Freescale
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MCM62486BFN11 Datasheet PDF : 12 Pages
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC, VCCQ = 5.0 V ± 5%, TA = 0 to + 70°C, for device MCM62486B–11)
(VCC = 5.0 V ± 10%, VCCQ = 5.0 V or 3.3 V ± 10%, TA = 0 to + 70°C, for all other devices)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . Figure 1A Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)
62486B–11
62486B–12
62486B–14
62486B–19
Parameter
Symbol Min Max Min Max Min Max Min Max Unit Notes
Cycle Time
tKHKH
15
—
20
—
20
—
25
—
ns
Clock Access Time
tKHQV
—
11
—
12
—
14
—
19
ns
Output Enable Access
tGLQV
—
5
—
5
—
6
—
7
ns
Clock High to Output Active
tKHQX1
6
—
6
—
6
—
6
—
ns
Clock High to Q Change
tKHQX2
3
—
3
—
4
—
4
—
ns
Output Enable to Q Active
tGLQX
0
—
0
—
0
—
0
—
ns
Output Disable to Q High–Z
tGHQZ
—
6
—
6
—
6
—
7
ns
4
Clock High to Q High–Z
tKHQZ
—
6
—
6
—
6
—
6
ns
Clock High Pulse Width
tKHKL
5.5 —
7
—
8
—
6
—
ns
Clock Low Pulse Width
tKLKH
5.5 —
7
—
8
—
6
—
ns
Setup Times:
Address tAVKH
2
—
2
—
3
—
3
—
ns
5
Address Status tADSVKH
Data In tDVKH
Write tWVKH
Address Advance tADVVKH
Chip Select tS0VKH
tS1VKH
Hold Times:
Address tKHAX
2
—
2
—
2
—
2
—
ns
5
Address Status tKHADSX
Data In tKHDX
Write tKHWX
Address Advance tKHADVX
Chip Select tKHS0X
tKHS1X
NOTES:
1. A read cycle is defined by W high or ADSP low for the setup and hold times. A write cycle is defined by W low and ADSP high for the setup
and hold times.
2. All read and write cycle timings are referenced from K or G.
3. G is a don’t care when W is sampled low.
4. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At any
given voltage and temperature, tKHQZ max is less than tKHQX1 min for a given device and from device to device.
5. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of clock (K) whenever ADSP
and ADSC are low and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges
of K when the chip is selected.Chip select must be true (S1 low and S0 high) at each rising edge of clock for the device (when ADSP or ADSC
is low) to remain enabled. Timings for S1 and S0 are similar.
AC TEST LOADS
+5V
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
OUTPUT
255 Ω
480 Ω
5 pF
VL = 1.5 V
Figure 1A
Figure 1B
MOTOROLA FAST SRAM
MCM62486B
5
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