MCM62486BFN11 Просмотр технического описания (PDF) - Motorola => Freescale

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MCM62486BFN11

32K x 9 Bit BurstRAM Synchronous Static RAM

Motorola => Freescale 

K

ADSC

ADSP

A0 – A14

BLOCK DIAGRAM (See Note)

ADV

BURST LOGIC

Q0

A0

Q1

CLR

A1

INTERNAL

A0′ ADDRESS

15

A1′

32K x 9

MEMORY

ARRAY

ADDRESS

REGISTER

A1 – A0

15

2

A2 – A14

9

9

WRITE

W

REGISTER

DATA–IN

REGISTERS

S0

ENABLE

S1

REGISTER

OUTPUT

BUFFER

G

9

DQ0 – DQ8

NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the

next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is per-

formed using the new external address. When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is

interrupted and a read or write (dependent on W) is performed using the new external address. Chip selects (S0, S1) are

sampled only when a new base address is loaded. After the first cycle of the burst, ADV controls subsequent burst cycles.

When ADV is sampled low, the internal address is advanced prior to the operation. When ADV is sampled high, the internal

address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the

address will wrap around to its initial state. See BURST SEQUENCE TABLE.

BURST SEQUENCE TABLE (See Note)

External Address

A14 – A2

A1

A0

1st Burst Address

A14 – A2

A1

A0

2nd Burst Address

A14 – A2

A1

A0

3rd Burst Address

A14 – A2

A1

A0

NOTE: The burst wraps around to its initial state upon completion.

MCM62486B

2

MOTOROLA FAST SRAM

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