CY7C68000 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C68000 Datasheet PDF : 14 Pages
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CY7C68000
56-pin SSOP
1 CLK
2 DataBus16_8
3 Uni_Bidi
4 GND
5 TXValid
6 VCC
7 ValidH
8 TXReady
9 Suspend
10 Reset
11 AVCC
12 XTALOUT
13 XTALIN
14 AGND
15 AVCC
16 DPLUS
17 DMINUS
18 AGND
19 XcvrSelect
20 TermSelect
21 OpMode0
22 OpMode1
23 GND
24 VCC
25 LineState0
26 LineState1
27 GND
28 RXValid
D0 56
D1 55
Reserved 54
D2 53
VCC 52
D3 51
D4 50
GND 49
D5 48
Reserved 47
D6 46
D7 45
D8 44
D9 43
Reserved 42
D10 41
D11 40
VCC 39
D12 38
GND 37
D13 36
VCC 35
D14 34
D15 33
Reserved 32
Reserved 31
RXError 30
RXActive 29
Figure 5-2. CY7C68000 56-pin SSOP Pin Assignment
5.1 CY7C68000 Pin Descriptions
Table 5-1. Pin Descriptions [1]
SSOP QFN
Name
Type Default
Description
11 4 AVCC
15 8 AVCC
14 7 AGND
Power
Power
Power
N/A Analog VCC. This signal provides power to the analog section of the chip.
N/A Analog VCC. This signal provides power to the analog section of the chip.
N/A Analog Ground. Connect to ground with as short a path as possible.
18 11 AGND
Power N/A Analog Ground. Connect to ground with as short a path as possible.
16 9 DPLUS
I/O/Z
Z USB DPLUS Signal. Connect to the USB DPLUS signal.
17 10 DMINUS
I/O/Z
Z USB DMINUS Signal. Connect to the USB DMINUS signal.
Note:
1. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs that are three-statable should only be pulled up or down to ensure
signals at power-up and in standby.
Document #: 38-08016 Rev. *H
Page 4 of 14
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