CY7C68000 Просмотр технического описания (PDF) - Cypress Semiconductor

Номер в каталоге

Компоненты Описание

Список матч

CY7C68000

TX2™ USB 2.0 UTMI Transceiver

Cypress Semiconductor 

CY7C68000

2.0 Applications

• DSL modems

• ATA interface

• Memory card readers

• Legacy conversion devices

• Cameras

• Scanners

• Home PNA

• Wireless LAN

• MP3 players

• Networking

3.0 Functional Overview

3.1 USB Signaling Speed

TX2 operates at two of the rates defined in the USB Specifi-

cation 2.0, dated April 27, 2000:

• Full speed, with a signaling bit rate of 12 Mbps

• High speed, with a signaling bit rate of 480 Mbps

TX2 does not support the low-speed (LS) signaling rate of 1.5

Mbps.

3.2 Transceiver Clock Frequency

TX2 has an on-chip oscillator circuit that uses an external 24-

MHz (±100-ppm) crystal with the following characteristics:

• Parallel resonant

• Fundamental mode

• 500-μW drive level

• 27–33 pF (5% tolerance) load capacitors

An on-chip phase-locked loop (PLL) multiplies the 24-MHz

oscillator up to 30/60 MHz, as required by the transceiver

parallel data bus. The default UTMI interface clock (CLK)

frequency is determined by the DataBus16_8 pin.

3.3 Buses

The two packages allow for 8/16-bit bidirectional data bus for

data transfers to a controlling unit.

3.4 Reset Pin

An input pin (Reset) resets the chip. This pin has hysteresis

and is active HIGH according to the UTMI specification. The

internal PLL stabilizes approximately 200 μs after VCC has

reached 3.3V.

3.5 Line State

The Line State output pins LineState[1:0] are driven by combi-

national logic and may be toggling between the J and the K

states. They are synchronized to the CLK signal for a valid

signal. On the CLK edge the state of these lines reflect the

state of the USB data lines. Upon the clock edge the 0-bit of

the LineState pins is the state of the DPLUS line and the one

bit of LineState is the DMINUS line. When synchronized, the

set up and hold timing of the LineState is identical to the

parallel data bus.

3.6 Full-speed vs. High-speed Select

The FS vs. HS is done through the use of both XcvrSelect and

the TermSelect input signals. The TermSelect signal enables

the 1.5 K ohm pull up on to the DPLUS pin. When TermSelect

is driven LOW, a SE0 is asserted on the USB providing the HS

termination and generating the HS Idle state on the bus. The

XcvrSelect signal is the control which selects either the FS

transceivers or the HS transceivers. To select the HS trans-

ceivers, set this pin to ‘0’. To select the FS transceivers, set

this pin to ‘1’.

3.7 Operational Modes

The operational modes are controlled by the OpMode signals.

The OpMode signals are capable of inhibiting normal

operation of the transceiver and evoking special test modes.

These modes take effect immediately and take precedence

over any pending data operations. The transmission data rate

when in OpMode depends on the state of the XcvrSelect

input.

OpMode[1:0]

Mode

Description

00

0

Normal operation

01

1

Non-driving

10

2

Disable Bit Stuffing and

NRZI encoding

11

3

Reserved

Mode 0 allows the transceiver to operate with normal USB

data decoding and encoding.

Mode 1 allows the transceiver logic to support a soft

disconnect feature which three-states both the HS and FS

transmitters, and removes any termination from the USB,

making it appear to an upstream port that the device has been

disconnected from the bus.

Mode 2 disables Bit Stuff and NRZI encoding logic so 1s

loaded from the data bus becomes Js on the DPLUS/DMINUS

lines and 0s become Ks.

4.0 DPLUS/DMINUS Impedance Termination

The CY7C68000 does not require external resistors for USB

data line impedance termination or an external pull up resistor

on the DPLUS line. These resistors are incorporated into the

part. They are factory trimmed to meet the requirements of

USB 2.0. Incorporating these resistors also reduces the pin

count on the part.

Document #: 38-08016 Rev. *H

Page 2 of 14

Share Link: