CY7C68000-56LFC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C68000-56LFC Datasheet PDF : 14 Pages
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PRELIMINARY
CY7C68000
Table 5-1. Pin Descriptions (continued)[1]
SSOP QFN
Name
2 51 DataBus16_8
13 6 XTALIN
12 5 XTALOUT
3 52 Uni_Bidi
6
55 VCC
24 17 VCC
35 28 VCC
39 32 VCC
52 45 VCC
Type
Input
Input
Output
Input
Power
Power
Power
Power
Power
Default
N/A
N/A
N/A
N/A
N/A
N/A
Description
Data Bus 16_8. Selects between 8- and 16-bit data transfers.
1–16-bit data path operation enabled. CLK = 30 MHz.
0–8-bit data path operation enabled. When Uni_Bidi = 0, D[8:15] are unde-
fined. When Uni_Bidi =1, D[0:7] are valid on TxValid and D[8:15] are valid
on RxValid. CLK = 60 MHz
Note: DataBus16_8 is static after Power-on Reset (POR) and is only sam-
pled at the end of Reset.
Crystal Input. Connect this signal to a 24-MHz parallel-resonant, funda-
mental mode crystal and 20-pF capacitor to GND.
It is also correct to drive XTALIN with an external 24-MHz square wave
derived from another clock source.
Crystal Output. Connect this signal to a 24-MHz parallel-resonant, funda-
mental mode crystal and 30-pF (nominal) capacitor to GND. If an external
clock is used to drive XTALIN, leave this pin open.
Driving this pin HIGH enables the unidirectional mode when the 8-bit
interface is selected. Uni_Bidi is static after power on reset (POR).
VCC. Connect to 3.3V power source.
VCC. Connect to 3.3V power source.
VCC. Connect to 3.3V power source.
VCC. Connect to 3.3V power source.
VCC. Connect to 3.3V power source.
4 53 GND
23 16 GND
27 20 GND
37 30 GND
49 42 GND
Ground N/A Ground.
Ground N/A Ground.
Ground N/A Ground.
Ground N/A Ground.
Ground N/A Ground.
31 24 Reserved
54 47 Reserved
47 40 Reserved
42 35 Reserved
32 25 Reserved
INPUT
INPUT
INPUT
INPUT
INPUT
Connect pin to Ground.
Connect pin to Ground.
Connect pin to Ground.
Connect pin to Ground.
Connect pin to Ground.
Document #: 38-08016 Rev. *E
Page 7 of 14
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