CY7C68000-56LFC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C68000-56LFC Datasheet PDF : 14 Pages
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PRELIMINARY
CY7C68000
Table 5-1. Pin Descriptions (continued)[1]
SSOP QFN
Name
56 49 D0
55 48 D1
53 46 D2
51 44 D3
50 43 D4
48 41 D5
46 39 D6
45 38 D7
44 37 D8
43 36 D9
41 34 D10
40 33 D11
38 31 D12
36 29 D13
34 27 D14
33 26 D15
1 50 CLK
10 3 Reset
19 12 XcvrSelect
20 13 TermSelect
9
2 Suspend
26 19 LineState1
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Output
Input
Input
Input
Input
Output
Default
Description
Bidirectional Data Bus. This bidirectional bus is used as the entire data
bus in the 8-bit bidirectional mode or the least significant eight bits in the 16-
bit mode or under the 8 bit uni-directional mode these bits are used as inputs
for data, selected by the RxValid signal.
Bidirectional Data Bus. This bidirectional bus is used as the upper eight
bits of the data bus when in the 16-bit mode, and not used when in the 8-bit
bidirectional mode. Under the 8 bit uni-directional mode these bits are used
as outputs for data, selected by the TxValid signal.
Clock. This output is used for clocking the receive and transmit parallel data
on the D[15:0] bus.
N/A Active HIGH Reset. Resets the entire chip. This pin can be tied to VCC
through a 0.1-µF capacitor and to GND through a 100K resistor for a 10
msec RC time constant.
N/A Transceiver Select. This signal selects between the Full Speed (FS) and
the High Speed (HS) transceivers:
0: HS transceiver enabled
1: FS transceiver enabled
N/A Termination Select. This signal selects between the between the Full
Speed (FS) and the High Speed (HS) terminations:
0: HS termination
1: FS termination
N/A Suspend. Places the CY7C68000 in a mode that draws minimal power from
supplies. Shuts down all blocks not necessary for Suspend/Resume opera-
tions. While suspended, TermSelect must always be in FS mode to ensure
that the 1.5 K ohm pull-up on DPLUS remains powered.
0: CY7C68000 circuitry drawing suspend current
1: CY7C68000 circuitry drawing normal current
Line State. These signals reflect the current state of the single-ended
receivers. They are combinatorial until a “usable” CLK is available then they
are synchronized to CLK. They directly reflect the current state of the
DPLUS (LineState0) and DMINUS (LineState1).
D- D+ Description
0 0 0: SE0
0 1 1: ‘J’ State
1 0 2: ‘K’ State
1 1 3: SE1
Document #: 38-08016 Rev. *E
Page 5 of 14
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