CY7C43684AV-10AC Просмотр технического описания (PDF) - Cypress Semiconductor

Номер в каталоге

Компоненты Описание

Список матч

CY7C43684AV-10AC

3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO with Bus Matching

Cypress Semiconductor 

CY7C43644AV

CY7C43664AV

CY7C43684AV

Almost Empty flag and Almost Full flag offset registers with

one of the three preset values listed in Table 3, the Serial

Program Mode (SPM) and at least one of the flag-select inputs

must be HIGH during the LOW-to-HIGH transition of its Master

Reset input (MRS1 and MRS2). For example, to load the

preset value of 64 into X1 and Y1, SPM, FS0, and FS1 must

be HIGH when FIFO1 reset (MRS1) returns HIGH. Flag-offset

registers associated with FIFO2 are loaded with one of the

preset values in the same way with Master Reset (MRS2).

When using one of the preset values for the flag offsets, the

FIFOs can be reset simultaneously or at different times.

To program the X1, X2, Y1, and Y2 registers in parallel from

Port A, perform a Master Reset on both FIFOs simultaneously

with SPM HIGH and FS0 and FS1 LOW during the LOW-to-

HIGH transition of MRS1 and MRS2. After this reset is

complete, the first four Writes to FIFO1 do not store data in

RAM but load the offset registers in the order Y1, X1, Y2, X2.

The Port A data inputs used by the offset registers are (A0–9),

(A0–11), or (A0–13), for the CY7C436X4AV, respectively. The

highest numbered input is used as the most significant bit of

the binary number in each case. Valid programming values for

the registers range from 0 to 1023 for the CY7C43644AV; 0 to

4095 for the CY7C43664AV; 0 to 16383 for the

CY7C43684AV.[2] After all the offset registers are programmed

from Port A, the Port B Full/Input Ready (FFB/IRB) is set HIGH

and both FIFOs begin normal operation.

To program the X1, X2, Y1, and Y2 registers serially, initiate a

Master Reset with SPM LOW, FS0/SD LOW, and FS1/SEN

HIGH during the LOW-to-HIGH transition of MRS1 and MRS2.

After this reset is complete, the X and Y register values are

loaded bit-wise through the FS0/SD input on each LOW-to-

HIGH transition of CLKA that the FS1/SEN input is LOW. Forty,

forty-eight, or fifty-six bit Writes are needed to complete the

programming for the CY7C436X4AV, respectively. The four

registers are written in the order Y1, X1, Y2, and, finally, X2.

The first-bit Write stores the most significant bit of the Y1

register and the last-bit Write stores the least significant bit of

the X2 register.

When the option to program the offset registers serially is

chosen, the Port A Full/Input Ready (FFA/IRA) flag remains

LOW until all register bits are written. FFA/IRA is set HIGH by

the LOW-to-HIGH transition of CLKA after the last bit is loaded

to allow normal FIFO1 operation. The Port B Full/Input ready

(FFB/IRB) flag also remains LOW throughout the serial

programming process, until all register bits are written. FFB/

IRB is set HIGH by the LOW-to-HIGH transition of CLKB after

the last bit is loaded to allow normal FIFO2 operation.

SPM, FS0/SD, and FS1/SEN function the same way in both

CY Standard and FWFT modes.

FIFO Write/Read Operation

The state of the Port A data (A0–35) lines is controlled by Port

A Chip Select (CSA) and Port A Write/Read Select (W/RA).

The A0–35 lines are in the high-impedance state when either

CSA or W/RA is HIGH. The A0–35 lines are active outputs

when both CSA and W/RA are LOW.

Data is loaded into FIFO1 from the A0–35 inputs on a LOW-to-

HIGH transition of CLKA when CSA is LOW, W/RA is HIGH,

ENA is HIGH, MBA is LOW, and FFA/IRA is HIGH. Data is read

from FIFO2 to the A0–35 outputs by a LOW-to-HIGH transition

of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH, MBA

is LOW, and EFA/ORA is HIGH (see Table 4). FIFO Reads and

Writes on Port A are independent of any concurrent Port B

operation.

The Port B control signals are identical to those of Port A with

the exception that the Port B Write/Read select (W/RB) is the

inverse of the Port A Write/Read select (W/RA). The state of

the Port B data (B0–35) lines is controlled by the Port B Chip

Select (CSB) and Port B Write/Read select (W/RB). The B0–35

lines are in the high-impedance state when either CSB is HIGH

or W/RB is LOW. The B0–35 lines are active outputs when CSB

is LOW and W/RB is HIGH.

Data is loaded into FIFO2 from the B0–35 inputs on a LOW-to-

HIGH transition of CLKB when CSB is LOW, W/RB is LOW,

ENB is HIGH, MBB is LOW, and FFB/IRB is HIGH. Data is

read from FIFO1 to the B0–35 outputs by a LOW-to-HIGH

transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is

HIGH, MBB is LOW, and EFB/ORB is HIGH (see Table 5).

FIFO Reads and Writes on Port B are independent of any

concurrent Port A operation.

The set-up and hold time constraints to the port clocks for the

port Chip Selects and Write/Read selects are only for enabling

Write and Read operations and are not related to high-

impedance control of the data outputs. If a port enable is LOW

during a clock cycle, the port’s Chip Select and Write/Read

select may change states during the set-up and hold time

window of the cycle.

When operating the FIFO in FWFT mode and the Output

Ready flag is LOW, the next word written is automatically sent

to the FIFO’s output register by the LOW-to-HIGH transition of

the port clock that sets the Output Ready flag HIGH, data

residing in the FIFO’s memory array is clocked to the output

register only when a Read is selected using the port’s Chip

Select, Write/Read select, Enable, and Mailbox select.

When operating the FIFO in CY Standard mode, data residing

in the FIFO’s memory array is clocked to the output register

only when a Read is selected using the port’s Chip Select,

Write/Read select, Enable, and Mailbox select.

Synchronized FIFO Flags

Each FIFO is synchronized to its port clock through at least two

flip-flop stages. This is done to improve flag-signal reliability by

reducing the probability of the metastable events when CLKA

and CLKB operate asynchronously to one another. EFA/ORA,

AEA, FFA/IRA, and AFA are synchronized to CLKA. EFB/

ORB, AEB, FFB/IRB, and AFB are synchronized to CLKB.

Table 6 and Table 7 show the relationship of each port flag to

FIFO1 and FIFO2.

Empty/Output Ready Flags (EFA/ORA, EFB/ORB)

These are dual-purpose flags. In the FWFT mode, the Output

Ready (ORA, ORB) function is selected. When the Output

Ready flag is HIGH, new data is present in the FIFO output

register. When the Output Ready flag is LOW, the previous

data word remains in the FIFO output register and any FIFO

reads are ignored.

In the CY Standard mode, the Empty Flag (EFA, EFB) function

is selected. When the Empty Flag is HIGH, data is available in

the FIFO’s RAM memory for reading to the output register.

When Empty Flag is LOW, the previous data word remains in

the FIFO output register and any FIFO reads are ignored.

The Empty/Output Ready flag of a FIFO is synchronized to the

port clock that reads data from its array. For both the FWFT

Document #: 38-06025 Rev. *C

Page 8 of 37

Share Link: